专利名称：Apparatus for the optimization of the
performances of real-time primitives of areal-time executive kernel onmultiprocessor architectures
发明人：DUCATEAU, MICHEL,POPESCU, DANIEL,SERS,
JEAN-MARIE
申请号：EP87402118.1申请日：19870923公开号：EP0264317A1公开日：19880420
专利附图：
摘要：The device comprises a real-time operator OTR formed by a microprogrammedcircuit connected to the BUS memory (Bc) which is common to the processors of themultiprocessor structure. As seen by a processor, this operator OTR behaves like acommon memory zone and possesses circuits for address recognition, for transmissionand reception of the data to be processed and for generating signals for monitoringexchanges. It consists of at least two stand-alone units (A1, A2) which are dedicatedrespectively to the management of certain real-time objects. These stand-alone unitsintercommunicate via a BUS (BUS OTR) internal to the operator. The invention applies inparticular to multimicroprocessor structures on board aircraft.
申请人：SOCIETE FRANCAISE D'EQUIPEMENTS POUR LA NAVIGATION AERIENNE(S.F.E.N.A.)
地址：Immeuble le Galilée Parc Tertiaire de Meudon 5/7 rue Jeanne Braconnier F-92366 Meudon la Forêt Cédex FR
国籍：FR
代理机构：Marquer, Francis
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