System Monitor Analog-to-Digital Converter Specification
Table 51:Analog-to-Digital Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
AVDD=2.5V±2%, VREFP=2.5V,VREFN=0V, ADCCLK=5.2MHz, TA=TMIN to TMAX, Typical values at TA=+25°CDC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode, and Common Mode = 0VResolution
Integral NonlinearityDifferential NonlinearityUnipolar Offset Error(1)Bipolar Offset Error(1)Gain Error(1)
Bipolar Gain Error(1)Total Unadjusted Error(Uncalibrated)Total Unadjusted Error(Calibrated)
Calibrated Gain Temperature Coefficient
DC Common-Mode RejectConversion Rate(2)
Conversion Time - ContinuousConversion Time - EventT/H Acquisition TimeDRP Clock FrequencyADC Clock FrequencyCLK Duty cycleAnalog Inputs(3)
Dedicated Analog InputsInput Voltage RangeVP - VN
Unipolar OperationDifferential Inputs
Unipolar Common Mode Range (FS input)Differential Common Mode Range (FS input) Bandwidth
Auxiliary Analog InputsInput Voltage Range
VAUXP[0] /VAUXN[0] to VAUXP[15] /VAUXN[15]
Unipolar OperationDifferential Operation
Unipolar Common Mode Range (FS input)Differential Common Mode Range (FS input)Bandwidth
Input Leakage CurrentInput Capacitance
On-chip Supply Monitor ErrorOn-chip Temperature Monitor Error
VCCINT and VCCAUX with calibration enabled–40°C to +125°C with calibration enabledA/D not converting, ADCCLK stopped
0–0.250+0.3
10±1.010
±1.0±4
0–0.250+0.3
20
1+0.25+0.5+0.7
kHzµApF% Reading
°C
1+0.25+0.5+0.7
MHzVoltsVolts
tCONVtCONVtACQDCLKADCCLK
Number of CLK cyclesNumber of CLK cyclesNumber of CLK cyclesDRP clock frequencyDerived from DCLK
48140
2505.260
MHzMHz%
26
3221
CMRRDC TUETUEINLDNL
No missing codes (TMIN to TMAX)Guaranteed MonotonicUncalibrated
Uncalibrated measured in bipolar mode Uncalibrated
Uncalibrated measured in bipolar modeDeviation from ideal transfer function.VREFP–VREFN=2.5V
Deviation from ideal transfer function.VREFP–VREFN=2.5V
Variation of FS code with temperatureVN = VCM=0.5V± 0.5V,VP–VN=100mV
±2±2±0.2±0.2±10±1±0.0170
±2
10
±2±0.9±30±30±2±2
BitsLSBsLSBsLSBsLSBs%%LSBsLSBsLSB/°CdB
DS202 (v5.5) June 17, 2016Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table58 shows the test setup parameters used for measuring input delay.Table 58:Input Delay Measurement Methodology
Description
I/O Standard Attribute
VL(1,2)000000
VH(1,2)3.03.32.51.81.51.2
Per PCI™ SpecificationPer PCI SpecificationPer PCI-X™ Specification
VREF–0.2VREF–0.2VREF–0.5VREF–0.5VREF–0.5VREF–0.5VREF–1.00VREF–0.75VREF–0.5
VREF+0.2VREF+0.2VREF+0.5VREF+0.5VREF+0.5VREF+0.5VREF+1.00VREF+0.75VREF+0.5
VREFVREFVREFVREFVREFVREFVREFVREFVREFVREF0(6)0(6)0(6)0(6)VMEAS(1,4,5)
1.41.651.250.90.750.6
VREF(1,3,5)
–––––––––0.801.00.750.900.901.081.51.250.90AGP Spec
LVTTL (Low-Voltage Transistor-Transistor Logic)LVTTLLVCMOS (Low-Voltage CMOS), 3.3VLVCMOS, 2.5VLVCMOS, 1.8VLVCMOS, 1.5VLVCMOS, 1.2V
PCI (Peripheral Component Interconnect), 33 MHz, 3.3VPCI, 66 MHz, 3.3VPCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)GTL Plus
HSTL (High-Speed Transceiver Logic), Class I & II
HSTL, Class III & IVHSTL, Class I & II, 1.8VHSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Transceiver Logic), Class I & II, 3.3VSSTL, Class I & II, 2.5VSSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
LVCMOS33LVCMOS25LVCMOS18LVCMOS15LVCMOS12PCI33_3PCI66_3PCIXGTLGTLP
HSTL_I, HSTL_IIHSTL_III, HSTL_IVHSTL_I_18, HSTL_II_18HSTL_III_18, HSTL_IV_18SSTL3_I,SSTL3_IISSTL2_I,SSTL2_IISSTL18_I,SSTL18_IIAGP
VREF–(0.2xVCCO)VREF+(0.2xVCCO)
1.2–0.1251.2–0.1250.6–0.1251.15–0.3
1.2+0.1251.2+0.1250.6+0.1251.15–0.3
LVDS (Low-Voltage Differential Signaling), 2.5VLVDS_25LVDSEXT (LVDS Extended Mode), 2.5VLDT (HyperTransport), 2.5V
LVDSEXT_25 LDT_25
LVPECL (Low-Voltage Positive Emitter-Coupled LVPECL_25Logic), 2.5V
Notes:
1.2.3.4.5.6.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCIstandards are the same for the corresponding non-DCI standards.Input waveform switches between VLand VH.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values listed are typical.
Input voltage level from which measurement starts.
This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure11.The value given is the differential input voltage.
DS202 (v5.5) June 17, 2016Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.5) June 17, 2016Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 78:Input Clock Tolerances
Symbol
Duty Cycle Input Tolerance (in %)TDUTYCYCRANGE_1TDUTYCYCRANGE_1_50TDUTYCYCRANGE_50_100TDUTYCYCRANGE_100_200TDUTYCYCRANGE_200_400TDUTYCYCRANGE_400
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
PSCLK onlyPSCLK and CLKIN
< 1MHz1 - 50MHz50 - 100MHz100 - 200MHz200 - 400MHz(4)
>400MHz
25-7525-7530-7040-6045-5545-55
%%%%%%
DescriptionFrequency RangeValueUnits
Speed Grade
-3
-2
-1
Units
DS202 (v5.5) June 17, 2016Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Attribute
CLKFX_MULTIPLYCLKFX_DIVIDE
Min21
Max3332
Table 83:DCM Switching Characteristics
Symbol
TDMCCK_PSEN/ TDMCKC_PSEN
TDMCCK_PSINCDEC/ TDMCKC_PSINCDECTDMCKO_PSDONE
Description
PSEN Setup/HoldPSINCDEC Setup/HoldClock to out of PSDONE
Speed Grade-31.200.001.200.001.00
-21.350.001.350.001.12
-11.560.001.560.001.30
Unitsnsnsns
DS202 (v5.5) June 17, 2016Product Specification
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