CS8416-DSZR资料

2024-10-18 来源：威能网

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CS8416

192 kHz Digital Audio Interface Receiver

Features

󰂍Complete EIAJ CP1201, IEC-60958, AES3,

󰂍32kHz to 192kHz Sample Frequency Range󰂍Low-Jitter Clock Recovery

󰂍Pin and Microcontroller Read Access to

S/PDIF-Compatible Receiver

󰂍+3.3V Analog Supply (VA)󰂍+3.3V Digital Supply (VD)

󰂍+3.3V or +5.0V Digital Interface Supply (VL)󰂍8:2 S/PDIF Input MUX

󰂍AES/SPDIF Input Pins Selectable in Hardware

Channel Status and User Data

󰂍SPI™ or I²C® Control Port Software Mode and

Stand-Alone Hardware Mode

󰂍Differential Cable Receiver

󰂍On-Chip Channel Status Data Buffer Memories󰂍Auto-Detection of Compressed Audio Input

Mode

󰂍Three General Purpose Outputs (GPO) Allow

Signal Routing

󰂍Selectable Signal Routing to GPO Pins󰂍S/PDIF-to-TX Inputs Selectable in Hardware

Streams

󰂍Decodes CD Q Sub-Code󰂍OMCK System Clock Mode

See the General Description and Ordering Informationon page2.

Mode

󰂍Flexible 3-wire Serial Digital Output Port

VAAGNDFILTRMCKVDVLDGNDOMCKRXNRXP0RXP1RXP2RXP3RXP4RXP5RXP6RXP7ReceiverClock&DataRecovery8:2MUXTX PassthroughMisc.ControlFormat DetectAES3S/PDIFDecoderDe-emphasis FilterC & U bit Data BufferControlPort&RegistersSerialAudioOutputOLRCKOSCLKSDOUTGPO0GPO1AD2/GPO2n:3MUXRSTSDA/SCL/AD1/AD0/CDOUTCCLKCDINCShttp://www.cirrus.comCopyright © Cirrus Logic, Inc. 2007

AUGUST '07

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CS8416

General Description

The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio dataaccording to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digitalaudio output port and comprehensive control ability through a selectable control port in Software Mode or throughselectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPOpins may be assigned to route a variety of signals to output pins.

A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream.Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins forchannel status data.

The CS8416 is available in 28-pin TSSOP, SOIC, and QFN packages in Commercial grade (-10° to +70°C) andAutomotive grade (-40° to +85°C). The CDB8416 Customer Demonstration board is also available for device eval-uation and implementation suggestions. Please refer to “Ordering Information” on page59 for complete orderinginformation.

Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, ef-fects processors, set-top boxes, and computer and automotive audio systems.

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CS8416

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS .....................................................................................6SPECIFIED OPERATING CONDITIONS...............................................................................................6ABSOLUTE MAXIMUM RATINGS.........................................................................................................6DC ELECTRICAL CHARACTERISTICS.................................................................................................7DIGITAL INPUT CHARACTERISTICS...................................................................................................7DIGITAL INTERFACE SPECIFICATIONS..............................................................................................7SWITCHING CHARACTERISTICS........................................................................................................8SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS...............................................................9SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE..................................................10SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT...............................................112. PIN DESCRIPTION - SOFTWARE MODE ..........................................................................................12

2.1 TSSOP Pin Description .................................................................................................................122.2 QFN Pin Description ......................................................................................................................143. PIN DESCRIPTION - HARDWARE MODE .........................................................................................16

3.1 TSSOP Pin Description .................................................................................................................163.2 QFN Pin Description ......................................................................................................................184. TYPICAL CONNECTION DIAGRAMS ................................................................................................205. APPLICATIONS ..................................................................................................................................22

5.1 Reset, Power-Down and Start-Up .................................................................................................225.2 ID Code and Revision Code ..........................................................................................................225.3 Power Supply, Grounding, and PCB Layout .................................................................................226. GENERAL DESCRIPTION ..................................................................................................................23

6.1 AES3 and S/PDIF Standards Documents .....................................................................................237. SERIAL AUDIO OUTPUT PORT .........................................................................................................23

7.1 Slip/Repeat Behavior .....................................................................................................................257.2 AES11 Behavior ............................................................................................................................268. S/PDIF RECEIVER ..............................................................................................................................27

8.1 8:2 S/PDIF Input Multiplexer .........................................................................................................27

8.1.1 General ...............................................................................................................................278.1.2 Software Mode ...................................................................................................................278.1.3 Hardware Mode ..................................................................................................................288.2 OMCK System Clock Mode ...........................................................................................................288.3 Clock Recovery and PLL Filter ......................................................................................................289. GENERAL PURPOSE OUTPUTS .......................................................................................................2910. ERROR AND STATUS REPORTING ................................................................................................30

10.1 General ........................................................................................................................................30

10.1.1 Software Mode .................................................................................................................3010.1.2 Hardware Mode ................................................................................................................3010.2 Non-Audio Detection ...................................................................................................................31

10.2.1 Format Detection ..............................................................................................................3110.3 Interrupts .....................................................................................................................................3111. CHANNEL STATUS AND USER-DATA HANDLING .......................................................................32

11.1 Software Mode ............................................................................................................................3211.2 Hardware Mode ...........................................................................................................................3212. CONTROL PORT DESCRIPTION .....................................................................................................33

12.1 SPI Mode .....................................................................................................................................3312.2 I²C Mode ......................................................................................................................................3413. CONTROL PORT REGISTER QUICK REFERENCE .......................................................................3514. CONTROL PORT REGISTER DESCRIPTIONS ..............................................................................36

14.1 Memory Address Pointer (MAP) ..................................................................................................3614.2 Control0 (00h) .............................................................................................................................3614.3 Control1 (01h) .............................................................................................................................37

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CS8416

14.4 Control2 (02h) .............................................................................................................................3814.5 Control3 (03h) .............................................................................................................................3914.6 Control4 (04h) .............................................................................................................................3914.7 Serial Audio Data Format (05h) ...................................................................................................4014.8 Receiver Error Mask (06h) .........................................................................................................4114.9 Interrupt Mask (07h) ....................................................................................................................4114.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h) .........................................................4114.11 Receiver Channel Status (0Ah) ................................................................................................4214.12 Format Detect Status (0Bh) .......................................................................................................4214.13 Receiver Error (0Ch) ................................................................................................................4314.14 Interrupt 1 Status (0Dh) ............................................................................................................4414.15 Q-Channel Subcode (0Eh - 17h) ...............................................................................................4414.16 OMCK/RMCK Ratio (18h) .......................................................................................................4514.17 Channel Status Registers (19h - 22h) .......................................................................................4514.18 IEC61937 PC/PD Burst Preamble (23h - 26h) ..........................................................................4514.19 CS8416 I.D. and Version Register (7Fh) ...................................................................................4515. HARDWARE MODE ..........................................................................................................................46

15.1 Serial Audio Port Formats ...........................................................................................................4615.2 Hardware Mode Function Selection ............................................................................................4615.3 Hardware Mode Equivalent Register Settings .............................................................................4716. EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ...................................................49

16.1 AES3 Receiver External Components ........................................................................................4916.2 Isolating Transformer Requirements ...........................................................................................4917. CHANNEL STATUS BUFFER MANAGEMENT ...............................................................................51

17.1 AES3 Channel Status (C) Bit Management ................................................................................5117.2 Accessing the E Buffer ................................................................................................................51

17.2.1 Serial Copy Management System (SCMS) ......................................................................51

18. PLL FILTER .......................................................................................................................................53

18.1 General ........................................................................................................................................5318.2 External Filter Components .........................................................................................................53

18.2.1 General .............................................................................................................................5318.2.2 Capacitor Selection ..........................................................................................................5418.2.3 Circuit Board Layout .........................................................................................................5418.2.4 Component Value Selection .............................................................................................5418.2.5 Jitter Attenuation ...............................................................................................................55

19. PACKAGE DIMENSIONS .................................................................................................................56TSSOP THERMAL CHARACTERISTICS.............................................................................................57QFN THERMAL CHARACTERISTICS.................................................................................................5820. ORDERING INFORMATION .............................................................................................................5921. REVISION HISTORY .........................................................................................................................60

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CS8416

LIST OF FIGURES

Figure 1. Audio Port Master Mode Timing...................................................................................................9Figure 2. Audio Port Slave Mode and Data Input Timing.............................................................................9Figure 3. SPI Mode Timing........................................................................................................................10Figure 4. I²C Mode Timing.........................................................................................................................11Figure 5. Typical Connection Diagram - Software Mode...........................................................................20Figure 6. Typical Connection Diagram - Hardware Mode..........................................................................21Figure 7. Serial Audio Output Example Formats........................................................................................24Figure 8. AES3 Data Format......................................................................................................................25Figure 9. Receiver Input Structure.............................................................................................................27Figure 10. C/U Data Outputs......................................................................................................................32Figure 11. Control Port Timing in SPI Mode..............................................................................................33Figure 12. Control Port Timing, I²C Slave Mode Write...............................................................................34Figure 13. Control Port Timing, I²C Slave Mode Read...............................................................................34Figure 14. De-Emphasis Filter Response..................................................................................................39Figure 15. Hardware Mode Data Flow.......................................................................................................46Figure 16. Professional Input Circuit..........................................................................................................49Figure 17. Transformerless Professional Input Circuit...............................................................................49Figure 18. Consumer Input Circuit.............................................................................................................50Figure 19. S/PDIF MUX Input Circuit.........................................................................................................50Figure 20. TTL/CMOS Input Circuit............................................................................................................50Figure 21. Channel Status Data Buffer Structure.......................................................................................52Figure 22. Flowchart for Reading the E Buffer...........................................................................................52Figure 23. PLL Block Diagram...................................................................................................................53Figure 24. Recommended Layout Example...............................................................................................54Figure 25. Jitter Attenuation Characteristics of PLL...................................................................................55

LIST OF TABLES

Table 1. Typical Delays by Frequency Values...........................................................................................26Table 2. Clock Switching Output Clock Rates............................................................................................28Table 3. GPO Pin Configurations...............................................................................................................29Table 4. Hardware Mode Start-Up Pin Conditions.....................................................................................47Table 5. Hardware Mode Serial Audio Format Select................................................................................48Table 6. External PLL Component Values.................................................................................................54

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CS8416

1.CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.

SPECIFIED OPERATING CONDITIONS

(AGND, DGND = 0V, all voltages with respect to 0V)

Parameter

Symbol Min Typ

Max

Units

Power Supply Voltage

Ambient Operating Temperature:

Commercial GradeAutomotive Grade

VAVDVLTA

3.133.133.13-10-40

3.33.33.3 or 5.0

3.463.465.25+70+85

VVV°C

ABSOLUTE MAXIMUM RATINGS

(AGND, DGND = 0V; all voltages with respect to 0V. Operation beyond these limits may result in permanent dam-age to the device. Normal operation is not guaranteed at these extremes.)

Parameter

Symbol

Min

Max

Units

Power Supply Voltage

Input Current, Any Pin Except SuppliesInput Voltage

Ambient Operating Temperature (power applied)Storage Temperature

Notes:

(Note 1)

VA, VD,VL

IinVinTATstg

---0.3-55-656.0±10(VL) + 0.3125150VmAV°C°C

1.Transient currents of up to 100mA will not cause SCR latch-up.

6DS578F3

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CS8416

DC ELECTRICAL CHARACTERISTICS

(AGND = DGND = 0V; all voltages with respect to 0V.)

Parameters

Power-Down Mode (Notes 2, 4)

Symbol

Min

Typ

Max

UnitsμAμAμAμA

Supply Current in power-down

VAVD

VL = 3.3VVL = 5.0VVAVD

VL = 3.3VVL = 5.0V

VAVD

VL = 3.3VVL = 5.0V

IAIDILILIAIDILILIAIDILIL

------------

107010125.75.92.84.29.4237.811.8

------------

Normal Operation (Notes 3, 4)

Supply Current at 48kHz frame rate

Supply Current at 192kHz frame rate

mAmAmAmAmAmAmAmA

Notes:

2.Power-Down Mode is defined as RST = LO with all clocks and data lines held static.3.Normal operation is defined as RST = HI.

4.Assumes that no inputs are floating. It is recommended that all inputs be driven high or low at all times.

DIGITAL INPUT CHARACTERISTICS

(AGND = DGND = 0V; all voltages with respect to 0V.)

Parameters

Symbol Min Typ

Max

UnitsμA

Input Leakage Current

Differential Input Sensitivity, RXP[7:0] to RXNInput Hysteresis

IINVTHVH

--0.15-150-±0.52001.0

mVppV

DIGITAL INTERFACE SPECIFICATIONS

(AGND = DGND = 0V; all voltages with respect to 0V.)

Parameters

Symbol Min Max

Units

High-Level Output Voltage (IOH = -3.2mA)Low-Level Output Voltage (IOL = 3.2mA)High-Level Input Voltage, except RXP[7:0], RXNLow-Level Input Voltage, except RXP[7:0], RXN

VOHVOLVIHVIL

(VL) - 1.0

-2.0-0.3

-0.5(VL) + 0.3

0.8

VVVV

DS578F37

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CS8416

SWITCHING CHARACTERISTICS

(Inputs: Logic 0 = 0V, Logic 1 = VL; CL = 20pF)

Parameter

Symbol

Min

Typ

Max

UnitsμS

RST Pin Low Pulse Width

PLL Clock Recovery Sample Rate RangeRMCK Output JitterRMCK Output Duty-Cycle

RMCK/OMCK Maximum Frequency

Notes:

20030-4550-

--2005055-

-200-556550

kHzpsRMS%%MHz

(Note 5)(Note 6)(Note 7)

5.Typical RMS cycle-to-cycle jitter.

6.Duty cycle when clock is recovered from biphase encoded input.7.Duty cycle when OMCK is switched over for output on RMCK.

8DS578F3

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CS8416

SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS

(Inputs: Logic 0 = 0V, Logic 1 = VL; CL = 20pF)

Parameter

Symbol

Min

Typ

Max

Units

OSCLK/OLRCK Active Edge to SDOUT Output Valid(Note 8)Master Mode

RMCK to OSCLK active edge delay(Note 8)RMCK to OLRCK delay(Note 9)OSCLK and OLRCK Duty CycleSlave ModeOSCLK Period

OSCLK Input Low WidthOSCLK Input High Width

OSCLK Active Edge to OLRCK Edge(Notes 8,9,10)OSCLK Edge Setup Before OSCLK Active-Edge(Notes 8,9,11)

Notes:

tdpdtsmdtlmd

-00-3614141010

---50-----

231212------

nsnsns%nsnsnsnsns

tsckwtsckltsckhtlrckdtlrcks

8.In Software Mode the active edges of OSCLK are programmable.9.In Software Mode the polarity of OLRCK is programmable.

10.This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK

has changed.11.This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.

OSCLK(output)OLRCK(input)tlrckdtlrckstsckhtscklOLRCK(output)tsmdRMCK(output)tOSCLK(input)tsckwlmdSDOUTtdpdFigure 1. Audio Port Master Mode TimingFigure 2. Audio Port Slave Mode and Data Input

DS578F39

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CS8416

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

(Inputs: Logic 0 = 0V, Logic 1 = VL; CL = 20pF)

Parameter

Symbol

Min

Max

Unit

CCLK Clock Frequency

CS High Time Between TransmissionsCS Falling to CCLK EdgeCCLK Low TimeCCLK High Time

CDIN to CCLK Rising Setup TimeCCLK Rising to DATA Hold TimeCCLK Falling to CDOUT StableRise Time of CDOUTFall Time of CDOUT

Rise Time of CCLK and CDINFall Time of CCLK and CDIN

Notes:

(Note 12)

fscktcshtcsstscltschtdsutdhtpdtr1tf1tr2tr2

01.02066664015-----

6.0------502525100100

MHzµsnsnsnsnsnsnsnsnsnsns

(Note 13)

(Note 14)(Note 14)

12.If Fs is lower than 46.875kHz, the maximum CCLK frequency should be less than 128Fs. This is dic-tated by the timing requirements necessary to access the Channel Status memory. Access to the con-trol register file can be carried out at the full 6MHz rate. The minimum allowable input sample rate is32kHz, so choosing CCLK to be less than or equal to 4.1MHz should be safe for all possible conditions.13.Data must be held for sufficient time to bridge the transition time of CCLK.14.For fsck <1MHz.

CStcssCCLKtr2CDINtdsutdhtf2tscltschtcshtpdCDOUTFigure 3. SPI Mode Timing

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CS8416

SWITCHING CHARACTERISTICS - CONTROL PORT- I²C FORMAT

(Inputs: Logic 0 = 0V, Logic 1 = VL; CL = 20pF)

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

Bus Free Time Between Transmissions

Start Condition Hold Time (prior to first clock pulse)Clock Low timeClock High Time

Setup Time for Repeated Start ConditionSDA Hold Time from SCL Falling(Note 15)SDA Setup time to SCL RisingRise Time of SCL and SDAFall Time SCL and SDA

Setup Time for Stop Condition

Notes:

fscltbufthdsttlowthightsustthddtsudtrtftsusp

-4.74.04.74.04.710250--4.7100-------1000300-kHzµsµsµsµsµsnsnsnsnsµs

15.Data must be held for sufficient time to bridge the 300ns transition time of SCL.

StopSDAtbufSCLStartRepeatedStartStopthdstthighthdsttftsusptlowthddtsudtsusttrFigure 4. I²C Mode Timing

DS578F311

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CS8416

2.PIN DESCRIPTION - SOFTWARE MODE

2.1

TSSOP Pin Description

RXP3RXP2RXP1RXP0RXNVAAGNDFILTRSTRXP4RXP5RXP6RXP7AD0 / CS

1234567891011121314Top-Down View28-pin SOIC/TSSOPPackage2827262524232221201918171615OLRCKOSCLKSDOUTOMCKRMCKVDDGNDVLGPO0GPO1AD2 / GPO2SDA / CDOUTSCL / CCLKAD1 / CDIN

Pin Name

VAVDVLAGNDDGND

Pin #

62321722

Pin Description

Analog Power (Input) - Analog power supply. Nominally +3.3V. This supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clockDigital Power (Input) – Digital core power supply. Nominally +3.3V

Logic Power (Input) – Input/Output power supply. Nominally +3.3V or +5.0V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-nected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected to a common ground area under the chip.

Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase.

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground. For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page53 for more information on the PLL and the external components.

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float-ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page49 for rec-ommended input circuits.

RST9

FILTRXP0RXP1RXP2RXP3RXP4RXP5RXP6RXP7

8432110111213

12DS578F3

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CS8416

Pin Name

RXN

Pin #Pin Description

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single-ended operation this should be AC coupled to ground through a capacitor. See “External AES3/SPDIF/IEC60958 Receiver Components” on page49 for recommended input circuits.

System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock. OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System Clock Mode” section on page28

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x through the RMCKF bit in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4 register (04h).

Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pinSerial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs)

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode.

Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out-put data from the control port interface on the CS8416. See the “Control Port Description” section on page33.

Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the “Control Port Description” section on page33.

Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416 into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the “Control Port Description” section on page33.

Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description” section on page33.

General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low through a 47kΩ resistor. See the “Control Port Description” section on page33 and “General Purpose Outputs” on page29 for GPO functions.

General Purpose Output 1 (Output) - See “General Purpose Outputs” on page29 for GPO functions.General Purpose Output 0 (Output) - See “General Purpose Outputs” on page29 for GPO functions.

OMCK25

RMCKOSCLKOLRCKSDOUTSDA / CDOUTSCL / CCLK

24272826

AD0 / CS14

AD1 / CDINAD2 / GPO2GPO1GPO0

181920

DS578F313

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CS8416

2.2

QFN Pin Description

SDOUT23OLRCKOSCLK2827262524OMCK22RXP1RXP2RXP3RXP0RXNVAAGNDFILTRSTRXP4

1234567Thermal Pad21201918171615RMCKVDDGNDVLGPO0GPO1AD2 / GPO2

Top-Down View28-pin QFN Package891011121314SCL / CCLKRXP5RXP6RXP7AD0 / CSAD1 / CDINPin Name

VAVDVLAGNDDGND

Pin #

32018419

Pin Description

Logic Power (Input) – Input/Output power supply. Nominally +3.3V or +5.0V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-nected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected to a common ground area under the chip.

RST6

FILT5

SDA / CDOUTDS578F3

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CS8416

Pin Name

RXP0RXP1RXP2RXP3RXP4RXP5RXP6RXP7RXN

Pin #

1282726789102

Pin Description

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode.

General Purpose Output 1 (Output) - See “General Purpose Outputs” on page29 for GPO functions.General Purpose Output 0 (Output) - See “General Purpose Outputs” on page29 for GPO functions.Thermal Pad - Thermal relief pad for optimized heat dissipation.

OMCK22

RMCKOSCLKOLRCKSDOUTSDA / CDOUTSCL / CCLK

21242523

AD0 / CS11

AD1 / CDINAD2 / GPO2GPO1GPO0THERMALPAD

151617-

DS578F315

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CS8416

3.PIN DESCRIPTION - HARDWARE MODE

3.1

TSSOP Pin Description

RXP3RXP2RXP1RXP0RXNVAAGNDFILTRSTRXSEL1RXSEL0TXSEL1TXSEL0NV / RERR

1234567891011121314Top-Down View28-pin SOIC/TSSOPPackage2827262524232221201918171615Pin Description

OLRCKOSCLKSDOUTOMCKRMCKVDDGNDVLTXCURCBL96KHZAUDIO

Pin Name

VAVDVLAGNDDGND

Pin #

62321722

Digital Power (Input) – Digital core power supply. Nominally +3.3V

Logic Power (Input) – Input/Output power supply. Nominally +3.3V or +5.0V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-nected to a common ground area under the chip.

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page53 for more information on the PLL and the external components.

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page49 for recommended input circuits.

RST9

FILT8

RXP0RXP1RXP2RXP34321

RXN5

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CS8416

Pin Name

OMCK

Pin #

Pin Description

System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK after reset. When enabled, the clock signal input on this pin is automatically output through RMCK on PLL unlock. See “OMCK System Clock Mode” on page28.

Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency is 256x the sample rate (Fs) when the U pin is pulled down by a 47kΩ resistor to DGND. Frequency is 128x the sample rate (Fs) when the U pin is pulled up by a 47kΩ resistor to VL.

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to DGND through a 47kΩ resistor to place the part in Hardware Mode.

Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input.TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out-put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs.

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected by a 47kΩ resistor to DGND. RERR is selected by a 47kΩ resistor to VL.

Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See “Non-Audio Detection” on page31. This pin is also used to select the serial port format (SFSEL1) at reset.

96kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1kHz. Otherwise the output is indeterminate. Also used to set the Emphasis Audio Match feature at reset.

Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set the serial audio port to master or slave at reset.

Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset.User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the frequency of RMCK to either 256*Fs or 128*Fs at reset.

RMCK24

OSCLKOLRCKSDOUTRXSEL1RXSEL0TXSEL1TXSEL0TX

2728261011121320

NV/RERRAUDIO

1415

96KHZ16

RCBL17

1918

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3.2

QFN Pin Description

SDOUT23OLRCKOSCLK2827262524OMCK22RXP1RXP2RXP3RXP0RXNVAAGNDFILTRSTRXSEL1

1234567Thermal Pad21201918171615RMCKVDDGNDVLTXCU

Top-Down View28-pin QFN Package891011121314TXSEL1RXSEL0TXSEL0NV / RERRAUDIOPin Name

VAVDVLAGNDDGND

Pin #

32018419

Pin Description

Digital Power (Input) – Digital core power supply. Nominally +3.3V

Logic Power (Input) – Input/Output power supply. Nominally +3.3V or +5.0V

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-nected to a common ground area under the chip.

PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground.

For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page53 for more information on the PLL and the external components.

RST6

FILT5

RXP0RXP1RXP2RXP31282726

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Pin Name

RXN

Pin #

Pin Description

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single-ended operation this should be AC coupled to ground through a capacitor. See “External AES3/SPDIF/IEC60958 Receiver Components” on page49 for recommended input circuits.System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK after reset. When enabled, the clock signal input on this pin is automatically output through RMCK on PLL unlock. See “OMCK System Clock Mode” on page28.

Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to DGND through a 47kΩ resistor to place the part in Hardware Mode.

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected by a 47kΩ resistor to DGND. RERR is selected by a 47kΩ resistor to VL.

OMCK22

RMCK21

OSCLKOLRCKSDOUTRXSEL1RXSEL0TXSEL1TXSEL0TX

2425237891017

NV/RERRAUDIO

1112

96KHZ13

RCBL14

CUTHERMAL PAD

1615-

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4.TYPICAL CONNECTION DIAGRAMS+3.3 V Analog SupplyFerrite *Bead+3.3 V+3.3 V or +5 V*10μF0.1μF0.1μF0.1μFVAVLRXNRXP0RXP1VDVLSDOUTOLRCKOSCLK47kΩSerial Audio Input Device**AES3 / S/PDIF SourcesRXP2RXP3RXP4RXP5RXP6CS8416RMCKOMCKClock ControlClock SourceVLRXP7AD0 / CSAD1 / CDINSCL / CCLKSDA / CDOUTRSTGPO0GPO1AD2/GPO2External InterfaceMicrocontrollerAGNDFILTRFLTDGNDCRIPCFLT**** A separate analog supply is only necessary in applications where RMCK is used for a jitter sensitive task. Forapplications where RMCK is not used for a jitter sensitive task, connect VA to VD via a ferrite bead. Keep decou-pling capacitors between VA and AGND.

** See “S/PDIF Receiver” on page27 and “External AES3/SPDIF/IEC60958 Receiver Components” on page49for typical input configurations and recommended input circuits.

*** For best jitter performance, connect the filter ground directly to the AGND pin. See Table6 on page54 for PLLfilter values.

Figure 5. Typical Connection Diagram - Software Mode

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Ferrite **Bead10μF0.1μF+3.3 V+3.3 V or +5 V0.1μF0.1μF+3.3 V Analog Supply**VAVLRXNAES3 / S/PDIF SourcesRXP0RXP1RXP2RXP3RSTVDVLOLRCKOSCLKSDOUTSerial Audio Input Device47kΩ***VLCS8416RXSEL0RXSEL1TXSEL0Hardware ControlTXSEL1NV/RERR*AUDIORCBL*U*C*AGNDFILTDGNDRMCKOMCKClock ControlClock SourceExternal Interface*TX*96KHZ*RFLTCRIPCFLT***** These pins must be pulled high to VL or low to DGND through a 47kΩ resistor.** A separate analog supply is only necessary in applications where RMCK is used for a jitter sensitive task. Forapplications where RMCK is not used for a jitter sensitive task, connect VA to VD via a ferrite bead. Keep decou-pling capacitors between VA and AGND.

*** See “S/PDIF Receiver” on page27 and “External AES3/SPDIF/IEC60958 Receiver Components” on page49for typical input configurations and recommended input circuits.

**** For best jitter performance connect the filter ground directly to the AGND pin. See Table6 on page54 for PLLfilter values.

Figure 6. Typical Connection Diagram - Hardware Mode

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5.APPLICATIONS

5.1

Reset, Power-Down and Start-Up

When RST is low, the CS8416 enters a low power mode and all internal states are reset, including the con-trol port and registers, and the outputs are muted. In Software Mode, when RST is high, the control portbecomes operational, and the desired settings should be loaded into the control registers. Writing a 1 to theRUN bit will then cause the part to leave the low power state and begin operation. After the PLL has settled,the serial audio outputs will be enabled.

Some options within the CS8416 are controlled by a start-up mechanism. During the reset state, some ofthe pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level of thesepins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used toset alternative modes in the CS8416 by connecting a 47kΩ resistor to between the pin and either VL (HI)or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-downresistor as there are no internal pull-up or pull-down resistors for these startup conditions (except for TX,which has an internal pull-down). In Software Mode, the only start-up option pins are GPO2, which are usedto set a chip address bit for the control port in I²C Mode, and SDOUT, which selects between Hardware andSoftware Modes. The Hardware Mode uses many start-up options, which are detailed in Section 15.2 “Hard-ware Mode Function Selection” on page46.

5.2ID Code and Revision Code

The CS8416 has a register that contains a 4-bit code to indicate that the addressed device is a CS8416.This is useful when other CS84XX family members are resident in the same system, allowing common soft-ware modules.

The CS8416 4-bit revision code is also available. This allows the software driver for the CS8416 to identifywhich revision of the device is in a particular system, and modify its behavior accordingly. To allow for futurerevisions, it is strongly recommend that the revision code is read into a variable area within the microcon-troller, and used wherever appropriate as revision details become known.

5.3Power Supply, Grounding, and PCB Layout

For most applications, the CS8416 can be operated from a single +3.3V supply, following normal supplydecoupling practices (See Figures5 and 6). For applications where the recovered input clock, output on theRMCK pin, is required to be low jitter, then use a separate, quiet, analog +3.3V supply for VA, decoupledto AGND. Make certain that no digital traces are routed near VA, AGND, or FILT as noise may couple anddegrade performance. These pins should be well isolated from switching signals and other noise sources.VL sets the level for the digital inputs and outputs, as well as the AES/SPDIF receiver inputs.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decouplingcapacitors are recommended. Decoupling capacitors should be mounted on the same side of the board asthe CS8416 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8416as possible. See “PLL Filter” on page53 for layout recommendations for the PLL.

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6.GENERAL DESCRIPTION

The CS8416 is a monolithic CMOS device that receives and decodes audio data according to the AES3, IEC60958,S/PDIF, and EIAJ CP1201 interface standards.

The CS8416 provides an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal tobe routed to an output of the CS8416. Input data can be either differential or single-ended. A low jitter clock is re-covered from the incoming data using a PLL. The decoded audio data is output through a configurable, 3-wire serialaudio output port. The channel status and Q-channel subcode portion of the user data are assembled in registersand may be accessed through an SPI or I²C port.

Three General Purpose Output (GPO) pins are provided to allow a variety of signals to be accessed under softwarecontrol. In Hardware Mode, dedicated pins are used to select audio stream inputs for decoding and transmission toa dedicated TX pin. Hardware Mode also provides channel status and user data output pins.

Figures5 and 6 show the power supply and external connections to the CS8416 when configured for Software Modeand Hardware Mode. Please note that all I/O pins, including RXN and RXP[7:0], operate at the VL voltage.

6.1AES3 and S/PDIF Standards Documents

This document assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable tohave current copies of the AES3, IEC60958, and IEC61937 specifications on hand for easy reference.The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org or atwww.ansi.org. Obtain a copy of the latest IEC60958/61937 standard from ANSI or from the InternationalElectrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from theJapaneseElectronics Bureau.

Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digitalaudio specifications, but it should not be considered a substitute for the standards.

The paper An Understanding and Implementation of the SCMS Serial Copy Management System forDigitalAudio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from theAES as reprint 3518.

7.SERIAL AUDIO OUTPUT PORT

A 3-wire serial audio output port is provided. The port can be adjusted to suit the attached device by setting the con-trol registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolu-tion, left- or right-justification of the data relative to left/right clock, optional one-bit cell delay of the first data bit, thepolarity of the bit clock, and the polarity of the left/right clock. By setting the appropriate control bits, many formatsare possible.

Figure7 shows a selection of common output formats, along with the control bit settings. A special AES3 direct out-put format is included, which allows the serial output port access to the V, U, and C bits embedded in the serial audiodata stream. When using the part in AES3 direct-output format, the de-emphasis filter must be off (see Section 14.4on page 38). The P bit, which would normally be a parity bit, is replaced by a Z bit, which is used to indicate the startof each block. The received channel status block start signal is also available as the RCBL pin in Hardware Modeand through a GPO pin in Software Mode.

In master mode, the left/right clock (OLRCK) and the serial bit clock (OSCLK) are outputs, derived from the recov-ered RMCK clock. In slave mode, OLRCK and OSCLK are inputs. OLRCK is normally synchronous to the appropri-ate master clock, but OSCLK can be asynchronous and discontinuous if required. By appropriate phasing of OLRCKand control of the serial clocks, multiple CS8416’s can share one serial port. OLRCK should be continuous, but theduty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to

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clock all the data bits. When in slave mode, the serial audio output port cannot be set for right-justified data. TheCS8416 allows immediate mute of the serial audio output port audio data by the MUTESAO bit of Control Register1. For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-ChannelSerial Audio Interface: A Tutorial”, available at www.cirrus.com.

Left JustifiedOSCLK(Out)SDOUTOLRCKChannel AChannel BMSBLSBMSBLSBMSBOLRCKI²S(Out)Channel AChannel BOSCLKSDOUTMSBLSBMSBLSBMSBRight JustifiedOSCLK(Out)SDOUTOLRCKChannel AChannel BMSB ExtendedMSBLSBMSB ExtendedMSBLSBAES3Direct (Out)OLRCKOSCLKSDOUTLSBChannel AChannel BChannel AChannel BMSBVUCLSBMSBVUCLSBMSBVUCZLSBMSBVUCZFrame 191Frame 0SOMS*SOSF*SORES[1:0]*SOJUST*SODEL*SOSPOL*SOLRPOL*

Left-Justified

I²S

Right-JustifiedAES3 DirectXX1XXXXXXXXXXX110010010000000100

X = don’t care to match format, but does need to be set to the desired setting

* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit

Figure 7. Serial Audio Output Example Formats

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7.1

Slip/Repeat Behavior

When using the serial audio output port in slave mode with an OLRCK input that is asynchronous to theincoming AES3 data, the interrupt bit OSLIP (bit 5 in the Interrupt 1 Status register, 0Dh) is provided to in-dicate when repeated or dropped samples occur. Refer to Figure8 for the AES3 data format diagram.When the serial output port is configured as slave, depending on the relative frequency of OLRCK to theinput AES3 data (Z/X) preamble frequency, the data will be slipped or repeated at the output of the CS8416.After a fixed delay from the Z/X preamble (a few periods of the internal clock, which is running at 256Fs),the circuit will look back in time until the previous Z/X preamble and check which of the following conditionsoccurred:

1.If during that time, the internal data buffer was not updated, a slip has occurred. Data from the previous

frame will be output and OSLIP will be set to 1. Due to the OSLIP bit being “sticky,” it will remain 1 untilthe register is read. It will then be reset until another slip/repeat condition occurs.2.If during that time the internal data buffer did not update between two positive or negative edges (de-pending on OLRPOL) of OLRCK, a repeat has occurred. In this case, the buffer data was updated twice,so the part has lost one frame of data. This event will also trigger OSLIP to be set to 1. Due to the OSLIPbit being “sticky,” it will remain 1 until the register is read. It will then be reset until another slip/repeatcondition occurs.3.If during that time, it did see a positive edge on OLRCK (or negative edge if the SOLRPOL is set to 1)

no slip or repeat has happened. Due to the OSLIP bit being “sticky,” it will remain in its previous stateuntil either the register is read or a slip/repeat condition occurs.If the user reads OSLIP as soon as the event triggers, over a long period of time the rate of occurring INTwill be equal to the difference in frequency between the input AES data and the slave serial output LRCK.The CS8416 uses a hysteresis window when a slip/repeat event occurs. The slip/repeat is triggered whenan edge of OLRCK passes a window size from the beginning of the Z/X preamble. Without the hysteresiswindow, jitter on OLRCK with a frequency very close to Fs could slip back and forth, causing multiple slip/re-peat events. The CS8416 uses a hysteresis window to ensure that only one slip/repeat happens even withjitter on OLRCK

Frame 191Frame 0Frame 1XChannel ADataYChannel BDataZChannel ADataYChannel BDataXChannel ADataYChannel BDataPreamblesOLRCK (in slave mode)Figure 8. AES3 Data Format

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7.2

AES11 Behavior

When OLRCK is configured as a master, the positive or negative edge of OLRCK (depending on the settingof SOLRPOL in register 05h) will be within -1.0%(1/Fs) to 1.1%(1/Fs) from the start of the preamble X/Z. Inmaster mode, the latency through the part is dependent on the input sample frequency. The typical delaythrough the part from the beginning of the preamble to the active edge of OLRCK for the various samplefrequencies is given in Table1. In master mode without the de-emphasis filter engaged, the latency of theaudio data will be 3 frames.

Fs (kHz)

Delay (ns)

3244.148649619298.080.578.067.057.547.0

Table 1. Typical Delays by Frequency Values

When OLRCK is configured as a slave, any synchronized input within +/-28%(1/Fs) from the positive or neg-ative edge of OLRCK (depending on the setting of SOLRPOL in register 05h) will be treated as being sam-pled at the same time. Since the CS8416 has no control of the OLRCK in slave mode, the latency of thedata through the part will be a multiple of 1/Fs plus the delay between OLRCK and the preambles.Both of these conditions are within the tolerance range set forth in the AES11 standard.

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8.S/PDIF RECEIVER

The CS8416 includes an AES3/SPDIF digital audio receiver. The receiver accepts and decodes bi-phase encodedaudio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The re-ceiver consists of an analog differential input stage, driven through analog input pins RXP0 to RXP7 and a commonRXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel statusand user data. External components are used to terminate the incoming data cables and isolate the CS8416. Thesecomponents are detailed in “External AES3/SPDIF/IEC60958 Receiver Components” on page49. Figure9 showsthe input structure of thereceiver.

VL22 kΩ(22000/N) ΩRXNRXP[7:0]VL = 5.0 V: 2.3 kΩVL = 3.3 V: 3.0 kΩ+VL = 5.0 V: (1500 + 800/N) ΩVL = 3.3 V: (1500 + 1500/N) Ω-22 kΩAGND(22000/N) ΩIf RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX, N=1.If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX, N=2.If RXP[7:0] is not selected at all, N=0 (i.e. high impedance).

Figure 9. Receiver Input Structure

8.18.1.1

8:2 S/PDIF Input MultiplexerGeneral

The CS8416 employs a 8:2 S/PDIF input multiplexer to accommodate up to eight channels of input digitalaudio data. Digital audio data may be single-ended or differential. Differential inputs utilize RXP[7:0] anda shared RXN. Single ended signals are accommodated by using the RXP[7:0] inputs and AC couplingRXN to ground.

All active inputs to the CS8416 8:2 input multiplexer should be coupled through a capacitor as these inputsare biased at VL/2 when selected. These inputs are floating when not selected. Unused multiplexer inputsshould be left floating or tied to AGND. The recommended capacitor value is 0.01μF to 0.1μF. The rec-ommended dielectrics for the AC coupling capacitors are C0G or X7R.

The input voltage range for the input multiplexer is set by the I/O power supply pin, VL. The input voltageof the RXP[7:0] and RXN pins is also set by the level of VL. Input signals with voltage levels above VL orbelow DGND may degrade performance or damage the part.

8.1.2Software Mode

The multiplexer select line control is accessed through bits RXSEL[2:0] in control port register 04h. Themultiplexer defaults to RXP0.

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The second output of the input multiplexer is used to provide the selected input as a source to be outputon a GPO pin. This pass through signal is selected by TXSEL[2:0] in control port register 04h. This single-ended signal is resolved to full-rail, but is not de-jittered before it is output.

8.1.3Hardware Mode

In Hardware Mode the input to the decoder is selected by dedicated pins, RXSEL[1:0].

The pass through signal is selected by dedicated pins, TXSEL[1:0] for output on the dedicated TX pin.This single-ended signal is resolved to full-rail, but is not de-jittered before it is output.

Selectable inputs are restricted to RXP0 to RXP3 for both the receiver and the TX output pin. These inputsare selected by RXSEL[1:0] and TXSEL[1:0] respectively.

8.2OMCK System Clock Mode

A special clock switching mode is available that allows the OMCK clock input to automatically replaceRMCK when the PLL becomes unlocked. This is accomplished without spurious transitions or glitches onRMCK. In Hardware Mode this feature is enabled by a transition (rising edge active) on the OMCK pin afterreset. Therefore to not enable the clock switching feature in Hardware Mode, OMCK should be tied to DGNDor VL. However, in Hardware Mode, once the clock switching feature has been enabled, it can only be dis-abled by resetting the part. In Software Mode the automatic clock switching feature is enabled by settingSWCLK bit in Control1 register to a “1”. Additionally in Software Mode, OMCK can be manually forced tooutput on RMCK by using the FSWCLK bit in the Control0 register.

When the clock switching feature is enabled, OSCLK and OLRCK are derived from the OMCK input whenthe clock has been switched and the serial port is in master mode. When clock switching is enabled and thePLL is not locked, OLRCK will be OMCK/256 and OSCLK will be OMCK/4. When the PLL loses lock, thefrequency of the VCO drops to ~750kHz. When this system clock mode is not enabled, the OSCLK andOLRCK will be based on the VCO when the PLL is not locked and has reached its steady-state idle frequen-cy. Table2 shows an example of output clocks based on clock switching being enabled or disabled.

Clock Switching Enabled/Disabled

DisabledEnabledDisabledEnabledDisabledEnabledDisabledEnabled

PLL

Locked/Unlocked

LockedLockedUnlockedUnlockedLockedLockedUnlockedUnlocked

RMCK Clock

Ratio

128*Fs128*Fs128*Fs128*Fs256*Fs256*Fs256*Fs256*Fs

RMCK

6.144MHz6.144MHz~375kHz11.2896MHz12.288MHz12.288MHz~750kHz11.2896MHz

OSCLK

3.072MHz3.072MHz~187.5kHz2.8224MHz3.072MHz3.072MHz~187.5kHz2.8224MHz

OLRCK

48kHz48kHz~2.925kHz44.1kHz48kHz48kHz~2.925kHz44.1kHz

Example with OMCK = 11.2896MHz, the receiver input sample rate = 48kHz, OSLCK = 64*Fs, and FSWCLK (Software Mode only) = ‘0’.

Table 2. Clock Switching Output Clock Rates

8.3Clock Recovery and PLL Filter

Please see “PLL Filter” on page53 for a general description of the PLL, selection of recommended PLL filtercomponents, and layout considerations. Figures5 and 6 show the recommended configuration of the twocapacitors and one resistor that comprise the PLL filter.

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9.GENERAL PURPOSE OUTPUTS

Three General Purpose Outputs (GPO) are provided to allow the equipment designer flexibility in configuring theCS8416. Fourteen signals are available to be routed to any of the GPO pins. The outputs of the GPO pins are setthrough the GPOxSEL[3:0] bits in the Control2 (02h) and Control3 (03h) registers. All GPO pins default to GNDafter reset.

GPO pins may be configured to provide the following data:

Function

GNDEMPHINTCURERRNVERRRCBL96KHZAUDIOVLRCKTXVDDHRMCK

Code

00000001001000110100010101100111100010011010101111001101

Fixed low level

Definition

State of EMPH bit in the incoming data stream.CS8416 interrupt outputChannel status bitUser data bitReceiver Error

Non-Validity Receiver ErrorReceiver Channel Status Block

If the input sample rate is ≤ 48kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1kHz. Otherwise the output is indeterminate.Non-audio indicator for decoded input stream

Virtual LRCK. Can be used to frame the C and U output data.

Pass through of AES/SPDIF input selected by TXSEL[2:0] in the Control 4 register (04h)VDD fixed high levelFS X 512 (Note 1)

Codes 1110 to 1111 - Reserved

Table 3. GPO Pin Configurations

Notes:

1.Frequency = 25MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ FS = 48kHz.

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10.ERROR AND STATUS REPORTING

10.1

General

While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify variouserror conditions.

10.1.1Software Mode

Software Mode allows the most flexibility in reading errors. When unmasked, bits in the Receiver Errorregister (0Ch) indicate the following errors:1.QCRC – CRC error in Q subcode data.2.CCRC – CRC error in channel status data.

3.UNLOCK – PLL is not locked to incoming data stream.4.V – Data Validity bit is set.

5.CONF – The logical OR of UNLOCK and BIP. The input data stream may be near error condition due

to jitter degradation.6.BIP – Biphase encoding error.7.PAR – Parity error in incoming data.

The error bits are “sticky,” meaning that they are set on the first occurrence of the associated error andwill remain set until the user reads the register through the control port. This enables the register to log allunmasked errors that occurred since the last time the register was read.

As a result of the bits “stickiness,” it is necessary to perform two reads on these registers to see if the errorcondition still exists.

The Receiver Error Mask register (06h) allows masking of individual errors. The bits in this register defaultto 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver errorregister, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audiosample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, whichdo not affect the current audio sample, even if unmasked.The HOLD bits allow a choice of:••OR•

Not changing the current audio sampleHolding the previous sample

Replacing the current sample with zero (mute)

10.1.2Hardware Mode

In Hardware Mode, the user may only choose between Non-Validity Receiver Error (NVERR) or ReceiverError (RERR) by pulling the NV/RERR pin low or high, respectively. The pull-up/pull-down condition willbe sensed on start-up, and the appropriate error reporting will be set.

RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit ishigh, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample.

NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi-phase, confidence or PLL lock error occurs during the current sample.

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10.2

Non-Audio Detection

An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in-coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit1, which is extracted automatically by the CS8416. However, certain non-audio sources, such as AC-3™ orMPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8416 AES3receiver can detect such non-audio data through the use of an autodetect module. The autodetect moduleis similar to autodetect software used in Cirrus Logic DSPs.

If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS® data transmission, aninternal AUTODETECT signal will be asserted. If the sync codes no longer appear after a certain amountof time, autodetection will time-out and AUTODETECT will be de-asserted until another format is detected.The AUDIO signal is the logical OR of AUTODETECT and the received channel status bit 1 (as decodedaccording to the CHS bit in the Control1 register).

In Hardware Mode, AUDIO is output on pin 15. In Software Mode, AUDIO is available through the GPO pins.If non-audio data is detected, the data is still processed exactly as if it were normal audio. The exception isthe use of de-emphasis auto-select feature which will bypass the de-emphasis filter if the input stream isdetected to be non-audio. It is up to the user to mute the outputs as required.

10.2.1Format Detection

In Software Mode, the CS8416 can automatically detect various serial audio input formats. The FormatDetect Status register (0Bh) is used to indicate a detected format. The register will indicate if uncom-pressed PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Addi-tionally, the IEC61937 Pc/Pd burst preambles are available in registers 23h-26h. See the registerdescriptions for more information.

10.3Interrupts

The CS8416 has a comprehensive interrupt capability. The INT signal, available in Software Mode, indi-cates when an interrupt condition has occurred and may be output on one of the GPOs. It can also be setthrough bits INT[1:0] in the Control1 register (01h) to be active low, active high or active low with no activepull-up transistor. This last mode is used for active low, wired-OR hook- ups, with multiple peripherals con-nected to the microcontroller interrupt input pin.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each sourcemay be masked off through mask register bits. In addition, each source may be set to rising edge, fallingedge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi-crocontroller, many different configurations are possible, depending on the needs of the equipment design-er. Refer to the register descriptions for the Interrupt Mask (07h), Interrupt Mode MSB (08h), Interrupt ModeLSB (09h), and Interrupt 1 Status (0Dh) registers

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11.CHANNEL STATUS AND USER-DATA HANDLING

“Channel Status Buffer Management” on page51 describes Channel Status and User data control.

11.1Software Mode

In Software Mode, several options are available for accessing the Channel Status and User data that is en-coded in the received AES3/SPDIF stream.

The first option allows access directly through registers. The first 5 bytes of the Channel Status block aredecoded into the Receiver Channel Status Registers 19h - 22h. Registers 19h - 1Dh contain the A channelstatus data. Registers 1Eh - 22h contain the B channel status data.

Received Channel Status (C), User (U), and EMPH bits may also be output to the GPO pins by appropriatelysetting the GPOxSEL bits in control port registers 02h and 03h. In serial port master mode, OLRCK andRCBL can be made available to qualify the U data output. In serial port slave mode, VLRCK and RCBL canbe made available to qualify the U data output. VLRCK is a virtual word clock, equal to the receiver recov-ered sample rate, that can be used to frame the C/U output. VLRCK and RCBL are available through theGPO pins. Figure10 illustrates timing of the C and U data and their related signals.

The user may also access all of the C and U bits directly from the output data stream (SDOUT) by settingbits SORES[1:0]=11 (AES3 Direct Mode) in the Serial Audio Data Format register (05h). The appropriatebits can be stripped from the SDOUT signal by external control logic such as a DSP or microcontroller.If the incoming User data bits have been encoded as Q-channel subcode, the data is decoded, buffered,and presented in 10 consecutive register locations (0Eh-17h). An interrupt may be enabled to indicate thedecoding of a new Q-channel block, which may be read through the control port.

The encoded Channel Status bits which indicate sample word length are decoded according to AES3-1992or IEC 60958. The number of auxiliary bits are reported in bits 7 to 4 of the Receiver Channel Status register(0Ah).

11.2Hardware Mode

In Hardware Mode, Received Channel Status (C), and User (U) bits are output on pins 19 and 18. In serialport master mode, OLRCK and RCBL are made available to qualify the C and U data output. Figure10 il-lustrates timing of the C and U data and their related signals.

The user may also access all of the C and U bits directly from the output data stream (SDOUT) by pullingthe AUDIO and C pins high through 47kΩ resistors to VL (AES3 Direct Mode). The appropriate bits can bestripped from the SDOUT signal by external control logic such as a DSP or microcontroller. Only OLRCK inmaster mode is available to qualify the U output. See “Hardware Mode Function Selection” on page46 and“Hardware Mode Equivalent Register Settings” on page47 to configure these pins..

RCBL(out)VLRCK(out)C/U(out)–––RCBL goes high 2 frames after receipt of a Z preamble and is high for 16 frames.VLRCK is a virtual work clock, available through the GPO pins, that can be used to frame the C/U output.

VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming

Figure 10. C/U Data Outputs

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12.CONTROL PORT DESCRIPTION

The control port is used to access the registers, allowing the CS8416 to be configured for the desired operationalmodes and formats. The operation of the control port may be completely asynchronous with respect to the audiosample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-eration is required.

The control port has 2 modes: SPI and I²C, with the CS8416 acting as a slave device. SPI Mode is selected if thereis a high to low transition on the AD0/CS pin, after the RST pin has been brought high. I²C Mode is selected by con-necting the AD0/CS pin through a resistor to VL or DGND, thereby permanently selecting the desired AD0 bit ad-dress state.

12.1SPI Mode

In SPI Mode, CS is the CS8416 chip select signal, CCLK is the control port bit clock (input into the CS8416from the microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data lineto the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure11 shows the operation of the control port in SPI Mode. To write to a register, bring CS low. The firstseven bits on CDIN form the chip address and must be 0010000. The eighth bit is a read/write indicator(R/W), which should be low to write. The next eight bits include the 7-bit Memory Address Pointer (MAP),which is set to the address of the register that is to be updated. The next eight bits are the data which willbe placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state.It may be externally pulled high or low with a 47kΩ resistor, if desired.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle whichfinishes (CS high) immediately after the MAP byte. To begin a read, bring CS low, send out the chip addressand set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressedregister (CDOUT will leave the high impedance state). The MAP automatically increments, so data for suc-cessive registers will appear consecutively.

CSCCLKCHIPADDRESSCDIN0010000R/WCHIPADDRESSLSBbytenMSBLSBMSBLSBMAPMSBDATA0010000R/Wbyte1HighImpedanceCDOUTMAP=MemoryAddressPointer,8bits,MSBfirstFigure 11. Control Port Timing in SPI Mode

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12.2

I²C Mode

In I²C Mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL. Thereis no CS pin. Pins AD0 and AD1 form the two least significant bits of the chip address and should be con-nected through a resistor to VL or DGND as desired. The GPO2 pin is used to set the AD2 bit by connectinga 47kΩ resistor from the GPO2 pin to VL or to DGND. The states of the pins are sensed while the CS8416is being reset.

The signal timings for a read and write cycle are shown in Figures12 and 13. A Start condition is definedas a falling transition of SDA while the clock is high. A Stop condition is a rising transition while the clock ishigh. All other transitions of SDA occur while the clock is low. The first byte sent to the CS8416 after a Startcondition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 4bits of the 7-bit address field are fixed at 0010. To communicate with a CS8416, the chip address field, whichis the first byte sent to the CS8416, should match 0010 followed by the settings of the AD2, AD1, and AD0pins. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte includes the Mem-ory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, thecontents of the register pointed to by the MAP will be output. The MAP automatically increments, so datafrom successive registers will appear consecutively. Each byte is separated by an acknowledge bit (ACK).The ACK bit is output from the CS8416 after each input byte is read, and is input to the CS8416 from themicrocontroller after each transmitted byte.

Note that the read operation can not set the MAP, so an aborted write operation is used as a preamble. Asshown in Figure13, the write operation is aborted after the acknowledge for the MAP byte by sending a stopcondition.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 24 252627 28SCLCHIP ADDRESS (WRITE)MAP BYTE 6 5 4 3 2 1 0 0ACKSTARTACKDATA7 6 1 0DATA +1 7 6 1 0DATA +n 7 6 1 0SDA0 0 1 0 AD2 AD1 AD0 0ACKACKSTOPFigure 12. Control Port Timing, I²C Slave Mode Write

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SCLCHIP ADDRESS (WRITE)MAP BYTE0ACKSTART6 5 4 3 2 1 0 STOPCHIP ADDRESS (READ)0 0 1 0 AD2 AD1 AD0 1DATA7 0DATA +17 0DATA + n7 0SDA0 0 1 0 AD2 AD1 AD0 0ACKSTARTACKACKNOACKSTOPFigure 13. Control Port Timing, I²C Slave Mode Read

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13.CONTROL PORT REGISTER QUICK REFERENCE

Addr R/W(HEX)

000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D

R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WRRRRRRRRRRRRRRRRRRRR

Function

Control0Control1Control2Control3Control4Serial Audio Data

FormatReceiver Error

MaskInterrupt MaskInterrupt Mode

MSBInterrupt Mode

LSBReceiver Channel

Status Audio Format

DetectReceiver ErrorInterrupt StatusQ-Channel Subcode [0:7]Q-Channel Subcode [8:15]Q-Channel Subcode [16:23]Q-Channel Subcode [24:31]Q-Channel Subcode [32:39]Q-Channel Subcode [40:47]Q-Channel Subcode [48:55]Q-Channel Subcode [56:63][Q-Channel Subcode 64:71]Q-Channel Subcode [72:79]OMCK_RMCK

RatioChannel A StatusChannel A StatusChannel A StatusChannel A StatusChannel A Status

0SWCLKDETCI

FSWCLKMUTSAO

0INT1

0INT0

PDURHOLD1

TRUNCHOLD0

ReservedRMCKF

ReservedCHS

EMPH_CNEMPH_CNEMPH_CNGPO0SEL3GPO0SEL2GPO0SEL1GPO0SEL0

TL2TL1TL0RXDSOSFQCRCMPCCHMPCCH1PCCH0AUX2PCMQCRCPCCH

RXSEL2SORES1CCRCMOSLIPMOSLIP1OSLIP0AUX1IEC61937CCRCOSLIP

RXSEL1SORES0UNLOCKMDETCMDETC1DETC0AUX0DTS_LDUNLOCKDETC

RXSEL0SOJUSTVMCCHMCCH1CCH0PRODTS_CD

VCCH

TXSEL2SODELCONFMRERRMRERR1RERR0COPYReservedCONFRERRADDRESSTRACKINDEXMINUTESECONDFRAMEZEROABS

MINUTEABS SECONDABS FRAMEORR2AC0[2]AC1[2]AC2[2]AC3[2]AC4[2]

TXSEL1SOSPOLBIPMQCHMQCH1QCH0ORIGDGTL_SIL

BIPQCHADDRESSTRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR1AC0[1]AC1[1]AC2[1]AC3[1]AC4[1]

TXSEL0SOLRPOLPARMFCHMFCH1FCH0EMPH96KHZPARFCHADDRESSTRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR0AC0[0]AC1[0]AC2[0]AC3[0]AC4[0]

GPO1SEL3GPO1SEL2GPO1SEL1GPO1SEL0GPO2SEL3GPO2SEL2GPO2SEL1GPO2SEL0

RUNSOMS0000AUX3000

CONTROLCONTROLCONTROLCONTROLADDRESSTRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR7AC0[7]AC1[7]AC2[7]AC3[7]AC4[7]

TRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR6AC0[6]AC1[6]AC2[6]AC3[6]AC4[6]

TRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR5AC0[5]AC1[5]AC2[5]AC3[5]AC4[5]

TRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR4AC0[4]AC1[4]AC2[4]AC3[4]AC4[4]

TRACKINDEXMINUTESECONDFRAMEZEROABS MINUTEABS SECONDABS FRAMEORR3AC0[3]AC1[3]AC2[3]AC3[3]AC4[3]

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Addr R/W(HEX)

1E1F202122232425267F

RRRRRRRRRR

Function

Channel B StatusChannel B StatusChannel B StatusChannel B StatusChannel B StatusBurst Preamble PC

Byte 0Burst Preamble PC

Byte 1Burst Preamble PD

Byte 0Burst Preamble PD

Byte 1ID & Version

BC0[7]BC1[7]BC2[7]BC3[7]BC4[7]PC0[7]PC1[7]PD0[7]PD1[7]ID3

BC0[6]BC1[6]BC2[6]BC3[6]BC4[6]PC0[6]PC1[6]PD0[6]PD1[6]ID2

BC0[5]BC1[5]BC2[5]BC3[5]BC4[5]PC0[5]PC1[5]PD0[5]PD1[5]ID1

BC0[4]BC1[4]BC2[4]BC3[4]BC4[4]PC0[4]PC1[4]PD0[4]PD1[4]ID0

BC0[3]BC1[3]BC2[3]BC3[3]BC4[3]PC0[3]PC1[3]PD0[3]PD1[3]VER3

BC0[2]BC1[2]BC2[2]BC3[2]BC4[2]PC0[2]PC1[2]PD0[2]PD1[2]VER2

BC0[1]BC1[1]BC2[1]BC3[1]BC4[1]PC0[1]PC1[1]PD0[1]PD1[1]VER1

BC0[0]BC1[0]BC2[0]BC3[0]BC4[0]PC0[0]PC1[0]PD0[0]PD1[0]VER0

14. CONTROL PORT REGISTER DESCRIPTIONS

14.1

Memory Address Pointer (MAP)

Not a register

6MAP6

5MAP5

4MAP4

3MAP3

2MAP2

1MAP1

0MAP0

MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.Default = ‘0000000’

14.2

Control0 (00h)

6FSWCLK

3PDUR

2TRUNC

1Reserved

0Reserved

FSWCLK – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK (Control1register bit 6) bit functionality or PLL lock.

Default = ‘0’

0 – Clock signal on OMCK is output on RMCK according to the SWCLK bit functionality.

1 – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK bit functionality.

PDUR – Changes the type of phase detector used to lock to the active RXP[7:0] input. This bit should onlybe set if the sample rate range is between 32kHz and 108kHz. If the sample rate is outside of this rangeand the PDUR bit is set, loss of lock may occur.

Default = ‘0’

0 – Normal Update Rate Phase Detector - Recovered master clock (RMCK) will have low wide-band jitter,but increased in-band jitter.

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1 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, butincreased wide-band jitter. Use this setting for the best performance when the output is connected to a delta-sigma digital-to-analog converter (DAC).

TRUNC – Determines if the audio word length is set according to the incoming channel status data as de-coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0].

Default = ‘0’

0 – Incoming data is not truncated.

1 – Incoming data is truncated according to the length specified in the channel status data.

Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data if de-emphasis filteris not used.

Reserved – These bits may change state depending on the input audio data.

14.3Control1 (01h)

MUTESAO

5INT1

4INT0

3HOLD1

2HOLD0

1RMCKF

0CHS

7SWCLK

SWCLK - Lets OMCK determine RMCK, OSCLK, OLRCK when PLL loses lock

Default = ‘0’

0 - Disable automatic clock switching. RMCK runs at the VCO frequency (~750kHz) on PLL Unlock.

1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK onPLL Unlock.

MUTESAO - Mute control for the serial audio output port

Default = ‘0’

0 - SDOUT not muted.

1 – SDOUT muted (set to all zeros).

INT[1:0] - Interrupt output pin (INT) control

Default = ‘00’

00 - Active high; high output indicates interrupt condition has occurred.01 - Active low, low output indicates an interrupt condition has occurred.

10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Thus it is not recommendedto multiplex INT onto GPO2 in I²C Control Port Mode since an external resistor is required on GPO2 to spec-ify the AD2 bit of the chip address.11 – Reserved.

HOLD[1:0] – Determine how received audio sample is affected when a receive error occurs

Default = ‘00’

00 – hold last audio sample.

01 – replace the current audio sample with all zeros (mute).10- do not change the received audio sample.11 - reserved

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RMCKF – Recovered Master Clock Frequency

Default = ‘0’

0 – RMCK output frequency is 256*FS.1 – RMCK output frequency is 128*FS.

CHS – Sets which channel's C data is decoded in the Receiver Channel Status register (0Ah).

Default = ‘0’0 – A channel.1 – B channel.

If CHS = 0 and TRUNC = 1, both channels' audio data will be truncated by the AUX[3:0] bits indicated in thechannel A Channel Status data. If CHS = 1 and TRUNC = 1, both channels' audio data will be truncated bythe AUX[3:0] bits indicated in the channel B Channel Status data. This will occur even if the AUX[3:0] bitsindicated in the channel A Channel Status data are not equal to the AUX[3:0] bits indicated in the channelB Channel Status data.

14.4Control2 (02h)

654

EMPH_CNTL2EMPH_CNTL1EMPH_CNTL0

GPO0SEL3

GPO0SEL2

GPO0SEL1

GPO0SEL0

7DETCI

DETCI – D to E status transfer inhibit

Default = ‘0’0 – Allow update.1 – Inhibit update.

EMPH_CNTL[2:0] – De-emphasis filter control. See Figure14 for De-emphasis filter response.

Default = ‘000’

000 – If the serial audio output port is using the AES3 direct-output format, the de-emphasis filter must re-main off.

001 – 32kHz setting.010 – 44.1kHz setting.011 – 48kHz setting.

100 – 50μs/15μs de-emphasis filter auto-select on. Coefficients (32, 44.1 or 48kHz or no de-emphasis fil-ter at all) match the pre-emphasis and sample frequency indicators in the channel status bits of Channel A.Thus it is impossible to have de-emphasis applied to one channel but not the other. The de-emphasis filteris turned off if the audio data is detected to be non-audio data.

GPO0SEL[3:0] – GPO0 Source select. See “General Purpose Outputs” on page29.

Default = ‘0000’

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Gain,dBT1 =50usT2=15us0-10F13.183F210.61Frequency,KHzFigure 14. De-Emphasis Filter Response

14.5Control3 (03h)

GPO1SEL2

GPO1SEL1

GPO1SEL0

GPO2SEL3

GPO2SEL2

GPO2SEL1

GPO2SEL0

GPO1SEL3

GPO1SEL[3:0] – GPO1 Source select. See “General Purpose Outputs” on page29.

Default = ‘0000’

GPO2SEL[3:0] – GPO2 Source select. See “General Purpose Outputs” on page29.

Default = ‘0000’

14.6Control4 (04h)

6RXD

5RXSEL2

4RXSEL1

3RXSEL0

2TXSEL2

1TXSEL1

0TXSEL0

7RUN

RUN - Controls the internal clocks, allowing the CS8416 to be placed in a “powered down”, low current con-sumption state.

Default = ‘0’

0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port isoperational,allowing registers to be read or changed. Power consumption is low.

1 - Normal part operation. This bit must be written to the 1 state to allow the CS8416 to begin operation.Allinput clocks should be stable in frequency and phase when RUN is set to 1.

RXD – RMCK Control

Default = ‘0’

0 -RMCK is an output, Clock is derived from input frame rate.

1 – RMCK becomes high impedance. The output of OSCLK, OLRCK, and SDOUT are indeterminate.

RX_SEL[2:0] – Selects RXP0 to RXP7 for input to the receiver

Default =’000’000 – RXP0001 – RXP1, etc

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TX_SEL[2:0] – Selects RXP0 to RXP7 as the input for GPO TX source

Default =’001’000 – RXP0001 – RXP1, etc

14.7Serial Audio Data Format (05h)

6SOSF

5SORES1

4SORES0

3SOJUST

2SODEL

1SOSPOL

SOLRPOL

7SOMS

SOMS - Master/Slave Mode Selector

Default = ‘0’

0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs. 1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs.

SOSF - OSCLK frequency (for master mode)

Default = ‘0’

0 - OSCLK output frequency is 64*Fs.1 - OSCLK output frequency is 128*Fs.

SORES[1:0] - Resolution of the output data on SDOUT

Default = ‘00’

00 - 24-bit resolution.01 - 20-bit resolution.10 - 16-bit resolution.

11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time slotoccupied by the Z bit is used to indicate the location of the block start. This setting forces the SOJUST bitto be “0”. When using this setting, the de-emphasis filter must be off.

SOJUST - Justification of SDOUT data relative to OLRCK

Default = ‘0’

0 - Left-Justified.

1 - Right-Justified (master mode only and SORES ≠11).

SODEL - Delay of SDOUT data relative to OLRCK, for Left-Justified data formats(This control is only valid in Left-Justified Mode)

Default = ‘0’

0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge.1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge.

SOSPOL - OSCLK clock polarity

Default = ‘0’

0 - SDOUT is sampled on rising edges of OSCLK.1 - SDOUT is sampled on falling edges of OSCLK.

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SOLRPOL - OLRCK clock polarity

Default = ‘0’

0 - SDOUT data is valid for the left channel when OLRCK is high.1 - SDOUT data is valid for the right channel when OLRCK is high.

14.8

Receiver Error Mask (06h)

6QCRCM

5CCRCM

UNLOCKM

3VM

2CONFM

1BIPM

0PARM

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a maskbit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register,will affect RERR, will affect the RERR interrupt, and will affect the current audio sample according to thestatus of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will notappear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and willnot affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: theydo not affect the current audio sample even when unmasked. This register defaults to 00h.

14.9

Interrupt Mask (07h)

6PCCHM

5OSLIPM

4DETCM

3CCHM

2RERRM

1QCHM

0FCHM

The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the erroris unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is setto 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status reg-ister. The bit positions align with the corresponding bits in Interrupt Status register. This register defaults to00h.

The INT signal may be selected to output on the GPO pins. See “General Purpose Outputs” on page29.

14.10Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)

700

6PCCH1PCCH0

5OSLIP1OSLIP0

4DETC1DETC0

3CCH1CCH0

2RERR1RERR0

1QCH1QCH0

0FCH1FCH0

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There arethree ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge activemode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode,the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interruptpin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) onlydepends on the INT[1:0] bits. These registers default to 00h.00 - Rising edge active01 - Falling edge active10 - Level active11 - Reserved

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14.11Receiver Channel Status (0Ah)

7AUX3

6AUX2

5AUX1

4AUX0

3PRO

2COPY

1ORIG

0EMPH

The bits in this register can be associated with either channel A or B of the received data. The desired chan-nel is selected with the CHS bit of the Control1 register.

AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded ac-cording to IEC60958 and AES3.

0000 - Auxiliary data is not present.0001 - Auxiliary data is 1 bit long.0010 - Auxiliary data is 2 bits long.0011 - Auxiliary data is 3 bits long.0100 - Auxiliary data is 4 bits long.0101 - Auxiliary data is 5 bits long.0110 - Auxiliary data is 6 bits long.0111 - Auxiliary data is 7 bits long.1000 - Auxiliary data is 8 bits long.1001 - 1111 Reserved

PRO - Channel status block format indicator

0 - Received channel status block is in the consumer format.1 - Received channel status block is in the professional format.

COPY - SCMS copyright indicator

0 - Copyright asserted.

1 - Copyright not asserted. If the category code is set to General in the incoming AES3 stream, copyrightwill always be indicated by COPY, even when the stream indicates no copyright.

ORIG - SCMS generation indicator, decoded from the category code and the L bit.

0 - Received data is 1st generation or higher.1 - Received data is original.

Note:

COPY and ORIG will both be set to 1 if incoming data is flagged as professional or if the receiveris not in use.

EMPH – Indicates whether the input audio data has been pre-emphasized. Also indicates turning on of thede-emphasis filter during de-emphasis auto-select mode.

0 – 50μs/15μs pre-emphasis indicated.1 – 50μs/15μs pre-emphasis not indicated.

14.12Format Detect Status (0Bh)

6PCM

5IEC61937

4DTS_LD

3DTS_CD

2Reserved

DGTL_SIL

096KHZ

Note:

PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the conditionwasdetected.

PCM – Uncompressed PCM data was detected.IEC61937 – IEC61937 data was detected.DTS_LD – DTS_LD data was detected.

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DTS_CD – DTS_CD data was detected.

Reserved – This bit may change state depending on the input audio data.

DGTL_SIL – Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bitaudio data on both channels.

96KHZ – If the input sample rate is ≤ 48kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥88.1kHz.Otherwise the output is indeterminate.

14.13Receiver Error (0Ch)

6QCRC

5CCRC

4UNLOCK

2CONF

1BIP

0PAR

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence ofthe error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the errorsource is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register.

QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries

0 - No error.1 - Error.

CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid in Promode

0 - No error.1 - Error.

UNLOCK - PLL lock status bit. Updated on CS block boundaries.

0 - PLL locked.1 - PLL out of lock.

V - Received AES3 Validity bit status. Updated on sub-frame boundaries.

0 - Data is valid and is normally linear coded PCM audio.1 - Data is invalid, or may be valid compressed audio.

CONF - Confidence bit. Updated on sub-frame boundaries.

0 - No error.

1 - Confidence error. The logical OR of UNLOCK and BIP. The input data stream may be near error condi-tion due to jitter degradation.

BIP - Bi-phase error bit. Updated on sub-frame boundaries.

0 - No error.

1 - Bi-phase error. This indicates an error in the received bi-phase coding.

PAR - Parity bit. Updated on sub-frame boundaries.

0 - No error.1 - Parity error.

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14.14Interrupt 1 Status (0Dh)

6PCCH

5OSLIP

4DETC

3CCH

2RERR

1QCH

0FCH

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once sincethe register was last read. A “0” means the associated interrupt condition has NOT occurred since the lastreading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level andthe interrupt source is still true. Status bits that are masked off in the associated mask register will alwaysbe “0” in this register.

PCCH – PC burst preamble change.

Indicates that the PC byte has changed from its previous value. If the IEC61937 bit in the Format DetectStatus register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the lasttime the IEC61937 bit went high.

OSLIP - Serial audio output port data slip interrupt

When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source,this bit will go high every time a data sample is dropped or repeated. See “Slip/Repeat Behavior” onpage25for more information.

DETC - D to E C-buffer transfer interrupt.

Indicates the completion of a D to E C-buffer transfer. See “Channel Status Buffer Management” onpage51.

C_CHANGE -Indicates that the current 10 bytes of channel status is different from the previous 10 bytes.(5 bytes per channel)

RERR - A receiver error has occurred.

The Receiver Error register may be read to determine the nature of the error which caused theinterrupt.

QCH – A new block of Q-subcode is available for reading. The data must be read within 588 AES3 framesafter the interrupt occurs to avoid corruption of the data by the next block.

FCH – Format Change: Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL bits in theFormat Detect Status register transition from 0 to 1. When these bits in the Format Detect Status registertransition from 1 to 0, an interrupt will not be generated.

14.15Q-Channel Subcode (0Eh - 17h)

76543210CONTROLCONTROLCONTROLCONTROLADDRESSADDRESSADDRESSADDRESSTRACKTRACKTRACKTRACKTRACKTRACKTRACKTRACKINDEXINDEXINDEXINDEXINDEXINDEXINDEXINDEXMINUTEMINUTEMINUTEMINUTEMINUTEMINUTEMINUTEMINUTESECONDSECONDSECONDSECONDSECONDSECONDSECONDSECONDFRAMEFRAMEFRAMEFRAMEFRAMEFRAMEFRAMEFRAMEZEROZEROZEROZEROZEROZEROZEROZEROABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS MINUTEABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS SECONDABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAMEABS FRAME

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus, bit 7 of address 0Eh is Q[0] whilebit 0 of address 0Eh is Q[7]. Similarly, bit 0 of address 17h corresponds to Q[79].

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14.16OMCK/RMCK Ratio (18h)

7ORR7

6ORR6

5ORR5

4ORR4

3ORR3

2ORR2

1ORR1

0ORR0

This register allows the calculation of the incoming sample rate by the host microcontroller from the equationORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256*Fso. ORR is rep-resented as an unsigned 2-bit integer and a 6-bit fractional part. The value is meaningful only after the PLLhas reached lock. For example, if the OMCK is 12.288MHz, Fso would be 48kHz (48kHz =12.288MHz/256). Then, if the input sample rate is also 48kHz, you would get 1.0 from the ORR register(The value from the ORR register is hexadecimal, so the actual value you will get is 40h).IfFSO/FSI>363/64, ORR will saturate at the value FFh. Also, there is no hysteresis on ORR. Therefore asmall amount of jitter on either clock can cause the LSB ORR[0] to oscillate.

ORR[7:6] - Integer part of the ratio (Integer value=Integer(SRR[7:6])).ORR[5:0] - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64).

14.17Channel Status Registers (19h - 22h)

19h1Ah1Bh1Ch1Dh1Eh1Fh20h21h22h

Channel A Status Byte 0Channel A Status Byte 1Channel A Status Byte 2Channel A Status Byte 3Channel A Status Byte 4Channel B Status Byte 0Channel B Status Byte 1Channel B Status Byte 2Channel B Status Byte 3Channel B Status Byte 4

AC0[7]AC1[7]AC2[7]AC3[7]AC4[7]BC0[7]BC1[7]BC2[7]BC3[7]BC4[7]

AC0[6]AC1[6]AC2[6]AC3[6]AC4[6]BC0[6]BC1[6]BC2[6]BC3[6]BC4[6]

AC0[5]AC1[5]AC2[5]AC3[5]AC4[5]BC0[5]BC1[5]BC2[5]BC3[5]BC4[5]

AC0[4]AC1[4]AC2[4]AC3[4]AC4[4]BC0[4]BC1[4]BC2[4]BC3[4]BC4[4]

AC0[3]AC1[3]AC2[3]AC3[3]AC4[3]BC0[3]BC1[3]BC2[3]BC3[3]BC4[3]

AC0[2]AC1[2]AC2[2]AC3[2]AC4[2]BC0[2]BC1[2]BC2[2]BC3[2]BC4[2]

AC0[1]AC1[1]AC2[1]AC3[1]AC4[1]BC0[1]BC1[1]BC2[1]BC3[1]BC4[1]

AC0[0]AC1[0]AC2[0]AC3[0]AC4[0]BC0[0]BC1[0]BC2[0]BC3[0]BC4[0]

14.18IEC61937 PC/PD Burst Preamble (23h - 26h)

23h24h25h26h

Burst Preamble PC Byte 0Burst Preamble PC Byte 1Burst Preamble PD Byte 0Burst Preamble PD Byte 1

PC0[7]PC1[7]PD0[7]PD1[7]

PC0[6]PC1[6]PD0[6]PD1[6]

PC0[5]PC1[5]PD0[5]PD1[5]

PC0[4]PC0[4]PC0[4]PD1[4]

PC0[3]PC1[3]PD0[3]PD1[3]

PC0[2]PC1[2]PD0[2]PD1[2]

PC0[1]PC1[1]PD0[1]PD1[1]

PC0[0]PC1[0]PD0[0]PD1[0]

14.19CS8416 I.D. and Version Register (7Fh)

7ID3

6ID2

5ID1

4ID0

3VER3

2VER2

1VER1

0VER0

ID[3:0] - ID code for the CS8416. Permanently set to 0010VER[3:0] = 0001 (revision A)VER[3:0] = 0010 (revision B)VER[3:0] = 0011 (revision C)VER[3:0] = 0111 (revision D)VER[3:0] = 1111 (revision E)

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15.HARDWARE MODE

The CS8416 has a Hardware Mode that allows the device to operate without a microcontroller. HardwareMode isselected by connecting the 47kΩ pull-up/down resistor on the SDOUT pin to ground. Various pins change functionin Hardware Mode, described in Section 15.2 “Hardware Mode Function Selection” on page46.

Hardware Mode data flow is shown in Figure15. Audio data is input through the AES3/SPDIF receiver, and routedto the serial audio output port. The decoded C and U bits are also output, clocked at both edges of OLRCK (mastermode only, see Figure10).

An error in the incoming audio stream will be indicated on the NV/RERR pin. This pin can be configured in one oftwo ways. If RERR is chosen by pulling NV/RERR to VL, the previous audio sample is held and passed to the serialaudio output port if the validity bit is high, or a parity, bi-phase, confidence or PLL lock error occurs during the currentsample. If NVERR is chosen by pulling NV/RERR to DGND, only parity, bi-phase, confidence or PLL lock errorcause the previous audio sample to be held.

15.1Serial Audio Port Formats

In Hardware Mode, only a limited number of alternative serial audio port formats are available. Table5 de-fines the equivalent Software Mode bit settings for each format.

The start-up options, shown in Table4, allow choice of the serial audio output port as a master or slave, andthe serial audio port format. RXSEL[1:0]TXSEL[1:0]OMCKRXP0RXP1RXP2RXP3RXNTX4:2MUXTX PassthroughAES3 Rx&DecoderDe-emphasisFilterSerialAudioOutputOLRCKOSCLKSDOUTCURMCKNV/RERR96kHzAUDIORCBLPower supply pins (VA, VD, and VL), AGND, DGND, the reset pin (RST) and the PLL filter pin (FILT)are omitted from the diagram. Please refer to the Typical Connection Diagram for connection details.Figure 15. Hardware Mode Data Flow

15.2Hardware Mode Function Selection

Hardware Mode and several options for Hardware Mode are selected by pulling CS8416 pins up to VL ordown to DGND through a 47kΩ resistor. These settings are sensed immediately after RST is released. For

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each mode, every start-up option select pin (except for TX, which has an internal pull-down) MUST have anexternal pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startupconditions (set after reset).

Pin Name

Pull Down to DGND Function

Pull Up to VL Function

SDOUTRCBLAUDIOCUTX96KHZNV/RERR

Hardware Mode

Serial Port Slave Mode

Serial Format Select 1 (SFSEL1)=0Serial Format Select 0 (SFSEL0)=0RMCK Frequency=256*Fs

Normal Phase Detector update rate.Emphasis Audio Match OffNVERR Selected

Software Mode

Serial Port Master Mode

Serial Format Select 1 (SFSEL1)=1Serial Format Select 0 (SFSEL0)=1RMCK Frequency=128*Fs

Higher Phase Detector update rate.Emphasis Audio Match OnRERR Selected

Table 4. Hardware Mode Start-Up Pin Conditions

15.3Hardware Mode Equivalent Register Settings

Listed below are the equivalent values that the registers are set to in Hardware Mode.

Control0 Register (00h)FSWCLK = 0

PDUR = Set by TX pin pull-up/down after reset.TRUNC = 0

Control1 Register (01h)

SWCLK = Set to 1 if there a transition on OMCK after reset. Otherwise set to 0.MUTSAO = 0INT[1:0] = N/A.HOLD[1:0] = 00

RMCKF = Set by U pin pull-up/down after reset.CHS = 0

Control2 Register (02h)DETCI = N/A

EMPH_CNTL[2] = set by 96KHZ pull-up/down after reset. See Figure14 for the de-emphasis filter re-sponse.

EMPH_CNTL[1:0] = 00GPO0SEL[3:0] = N/AControl3 Register (03h)GPO1SEL[3:0] = N/AGPO2SEL[3:0] = N/A

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Control4 Register (04h)RUN = 1RXD = 0RX_SEL[2] = 0

RX_SEL[1:0] = RX_SEL[1:0] pins.TX_SEL[2] = 0

TX_SEL[1:0] = TX_SEL[1:0] pins.Serial Audio Data Format Register (05h)SOMS = set by RCBL pull-up/down after reset.

bits[6:0] = Set by pull-up/down on AUDIO & C after reset. See Table5 for bit settings.

Serial Format Select [1:0]

SOSF

SORES[1:0]

SOJUST

SODEL

SOSPOLSOLRPOL

00 (Left-Justified 24-bit)01(I²S 24 bit)

10 (Right-Justified 24-bit)11 (Direct AES3)0000000000110010010000000100

Table 5. Hardware Mode Serial Audio Format Select

Receiver Error Mask register (06h)QCRCM = 0CRCM = 0UNLOCKM = 1CONFM = 1BIPM = 1PARM = 1

VM = set by NV/RERR pull-up/down after reset.

Registers 07h through 7Fh do not have Hardware Mode equivalent settings.

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16.EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS

16.1

AES3 Receiver External Components

The CS8416 AES3 receiver is designed to accept both the professional and consumer interfaces. The dig-ital audio specifications for professional use call for a balanced receiver, using XLR connectors, with110Ω±20% impedance. The XLR connector on the receiver should have female pins with a male shell.Since the receiver has a very high input impedance, a 110Ω resistor should be placed across the receiverterminals to match the line impedance, as shown in Figures16 and 17. Although transformers are not re-quired by the AES specification, they are strongly recommended.

If some isolation is desired without the use of transformers, a 0.01μF capacitor should be placed in serieswith each input pin (RXP[7:0] and RXN) as shown in Figure17. However, if a transformer is not used, highfrequency energy could be coupled into the receiver, causing degradation in analog performance.Figures16 and 17 show an optional (recommended) DC blocking capacitor (0.1μF to 0.47μF) in series withthe cable input. This improves the robustness of the receiver, preventing the saturation of the transformer,or any DC current flow, if a DC voltage is present on the cable.

In the case of the consumer interface, the standards call for an unbalanced circuit having a receiver imped-ance of 75Ω ±5%. The connector for the consumer interface is an RCA phono socket. The receiver circuitfor the consumer interface is shown in Figure18. An implementation of the Input S/PDIF Multiplexer usingthe consumer interface is shown in Figure19.

The circuit shown in Figure20 may be used when external RS422 receivers, optical receivers or otherTTL/CMOS logic outputs drive the CS8416 receiver section.

In the configuration of systems, it is important to avoid ground loops and DC current flowing down the shieldof the cable that could result when boxes with different ground potentials are connected. Generally, it isgood practice to ground the shield to the chassis of the transmitting unit, and connect the shield through acapacitor to chassis ground at the receiver. However, in some cases it is advantageous to have the groundof two boxes held to the same potential, and the cable shield might be depended upon to make that electricalconnection. Generally, it is a good idea to provide the option of grounding or capacitively coupling the shieldto the chassis.

16.2Isolating Transformer Requirements

Please refer to the application note AN134: AES and SPDIF Recommended Transformers for resources ontransformer selection.

XLR110ΩTwistedPair1* See Text110ΩCS8416RXP0XLR110ΩTwistedPair1CS8416*SeeText110Ω0.01μFRXP00.01μFRXNRXNFigure 16. Professional Input CircuitFigure 17. Transformerless Professional Input Circuit

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.01μF75ΩCoax75Ω.01μF75Ω.01μF75ΩCoax75ΩRXP6CS8416RXP7RCA Phono75ΩCoax75Ω0.01μFCS8416RXP075ΩCoax...RXP0RXN0.01μFRXN.01μFFigure 18. Consumer Input CircuitFigure 19. S/PDIF MUX Input Circuit

TTL/CMOSGate0.01μFCS8416RXP00.01μFRXNFigure 20. TTL/CMOS Input Circuit

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17.CHANNEL STATUS BUFFER MANAGEMENT

17.1

AES3 Channel Status (C) Bit Management

The CS8416 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels(5x2x8= 80 bits). The user may read from this buffer’s RAM through the control port.

The buffering scheme involves two buffers, named D and E, as shown in Figure21. The MSB of each byterepresents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control portaddress 19h) is the consumer/professional bit for channel status block A.

The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocksof data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the firstfive bytes of C data.

The complete C data may be obtained through the C pin in Hardware Mode and through one of the GPOpins in Software Mode. The C data is serially shifted out of the CS8416 clocked by the rising and fallingedges of OLRCK.

17.2Accessing the E Buffer

The user can monitor the incoming data by reading the E buffer, which is mapped into the register space ofthe CS8416, through the control port.

The user can configure the interrupt enable register to cause interrupts to occur whenever D to E buffertransfers occur. This allows determination of the allowable time periods to interact with the E buffer.Also provided is a D to E inhibit bit in the Control2 register (02h). This may be used whenever “long” controlport interactions are occurring or for debugging purposes.

A flowchart for reading the E buffer is shown in Figure22. Since a D to E interrupt occurs just after reading,there is a substantial time interval until the next D to E transfer (approximately 192 frames worth of time).This is usually enough time to access the E data without having to inhibit the next transfer.

17.2.1Serial Copy Management System (SCMS)

In Software Mode, the CS8416 allows read access to all the channel status bits. For consumer modeSCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit andL bit appropriately.

In Hardware Mode, the SCMS protocol can be followed by either using the COPY and ORIG output pins,or by using the C bit serial output pin. These options are documented in Section 15. “Hardware Mode” onpage46.

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A8-bitsFromAES3ReceiverReceivedDataBuffer5 words19 wordsB8-bitsControlPortRegistersDC Data Serial OutputEFigure 21. Channel Status Data Buffer Structure

DtoEinterruptoccursOptionallysetDtoEinhibitReadEdataIfset,clearDtoEinhibitReturnFigure 22. Flowchart for Reading the E Buffer

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18.PLL FILTER

18.1

General

An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure23is a simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it is updat-ed at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, FS.There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is impor-tant. For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shownin Figure25. In addition, the PLL has been designed to only use the preambles (PDUR=0) of the bi-phaseencoded stream to provide lock update information to the PLL. This results in the PLL being immune to datadependent jitter affects because the preambles do not vary with the data.

The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL willonly track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the samplerate that the PLL first locks onto upon application of an bi-phase encoded data stream or after enabling theCS8416 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will returnto its wide lock range mode and re-acquire a new nominal center sample rate.

INPUTPhaseComparatorand Charge PumpVCORFLTCFLTCRIPRMCK÷NFigure 23. PLL Block Diagram

18.2External Filter Components

18.2.1General

The PLL behavior is affected by the external filter component values. Figures5 and 6 shows the recom-mended configuration of the two capacitors and one resistor that comprise the PLL filter. In Table6, thecomponent values shown have a high corner frequency jitter attenuation curve, take a short time to lock,and offer good output jitter performance. Lock times are worst case for an Fsi transition of 192kHz.It is important to treat the PLL FLT pin as a low-level analog input. It is suggested that the ground end ofthe PLL filter be returned directly to the AGND pin independently of the ground plane.

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18.2.2Capacitor Selection

The type of capacitors used for the PLL filter can have a significant effect on receiver performance. Largeor exotic film capacitors are not necessary as their leads and the required longer circuit board traces addundesirable inductance to the circuit. Surface mount ceramic capacitors are a good choice because theirown inductance is low, and they can be mounted close to the FILT pin to minimize trace inductance. ForCRIP, a C0G or NPO dielectric is recommended, and for CFLT, an X7R dielectric is preferred. Avoid ca-pacitors with large temperature co-coefficient, or capacitors with high dielectric constants, that are sensi-tive to shock and vibration. These include the Z5U and Y5V dielectrics.

18.2.3Circuit Board Layout

Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure24contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage.The 0.1µF bypass capacitor is in a 1206 form factor. RFLT, CFLT, CRIP, and the 1000pF decoupling ca-pacitor are in an 0805 form factor. The traces are on the top surface of the board with the IC so that thereis no via inductance. The traces themselves are short to minimize the inductance in the filter path. TheVA and AGND traces extend back to their origin and are shown only in truncated form in the drawing.AGND1000pFCRIPRFLT.1µFCFLTFigure 24. Recommended Layout Example

18.2.4Component Value Selection

The external PLL component values are listed in Table6.

Range (kHz)

RFLTCFLT

FILTVACRIP

Settling Time

32 - 1923kΩ22nF1nF4 ms

Table 6. External PLL Component Values

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18.2.5Jitter Attenuation

Shown in Figure25 is the jitter attenuation plot. The AES3 and IEC60958-4 specifications state a maxi-mum of 2dB jitter gain or peaking. 420external Jitter Attenuation (dB)2468101211010010110Jitter Frequency (Hz)2103104105Figure 25. Jitter Attenuation Characteristics of PLLDS578F355

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19.PACKAGE DIMENSIONS

28L SOIC (300 MIL BODY) PACKAGE DRAWING

SEATINGPLANE

A1L

∝DIMMINA 0.093A10.004b0.013C0.009D0.697E0.291e0.040H0.394L0.016

0°∝INCHESNOM0.0980.0080.0170.0110.7050.2950.0500.4070.0264°

MAX0.1040.0120.0200.0130.7130.2990.0600.4190.0508°JEDEC #: MS-013

MIN2.350.100.330.2317.707.401.0210.000.400°

MILLIMETERSNOM2.500.200.420.2817.907.501.2710.340.654°

MAX2.650.300.510.3218.107.601.5210.651.278°

Controlling Dimension is Millimeters

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28L TSSOP (4.4mm BODY) PACKAGE DRAWING

E11

A2A1SEATINGPLANEA

SIDE VIEW

123

∝L

END VIEW

TOP VIEW

DIMAA1A2bDEE1eLµMIN--0.002 0.031500.007480.378 BSC0.2480.169--0.0200°

INCHESNOM--0.004 0.0350.00960.382 BSC0.25190.17320.026 BSC0.0244°

MAX0.470.006 0.040.0120.386 BSC0.2560.177--0.0298°MIN--0.050.800.199.60 BSC6.304.30--0.500°

MILLIMETERSNOM--0.100.900.2459.70 BSC6.404.400.65 BSC0.604°

NOTEMAX1.200.151.000.309.80 BSC6.504.50--0.758°

2,311

JEDEC #: MO-153

Controlling Dimension is Millimeters.

Notes:

1.“D” and “E1” are reference datums and do not include mold flash or protrusions, but do include mold

mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm perside.2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be

0.13mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re-duce dimension “b” by more than 0.07mm at least material condition.3.These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips.

TSSOP THERMAL CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Junction to Ambient Thermal Impedance4 Layer Board

θJA

-°C/Watt

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28-PIN QFN (5 × 5 MM BODY) PACKAGE DRAWING

DbePin #1 CornerPin #1 CornerEE2A1ALD2Top ViewSide ViewBottom ViewINCHESDIMAA1bDD2EE2eL

MIN--0.00000.0071

NOM----0.00910.1969 BSC0.12400.1969 BSC0.12400.0197 BSC0.0236

MAX0.03940.00200.0118

MIN--0.000.18

MILLIMETERSNOM----0.235.00 BSC3.155.00 BSC3.150.50 BSC0.60

MAX1.000.050.30

NOTE

0.12200.12200.0197

0.12600.12600.0276

3.103.100.50

3.203.200.70

111,2111111

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Notes:

1.Dimensioning and tolerance per ASME Y 14.5M-1995.

2.Dimensioning lead width applies to the plated terminal and is measured between 0.23mm and 0.28mm

from the terminal tip.

QFN THERMAL CHARACTERISTICS

Parameter

Symbol

Min

Typ

Max

Units

Junction to Ambient Thermal Impedance

2 Layer Board4 Layer Board

θJA

--13037--°C/Watt°C/Watt

58DS578F3

元器件交易网www.cecb2b.com

CS8416

20.ORDERING INFORMATION

Product

Description

Pb-Free

Grade

Temp Range

Package

Container

Order#

28-SOIC

Commercial

-10° to +70°C

28-TSSOP

28-QFN

CS8416

192 kHz Digital Audio Interface Receiver

YES

28-SOIC

Automotive

-40° to +85°C

28-TSSOP

28-QFN

CDB8416

Evaluation Board for

CS8416

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RailTape and ReelRailTape and ReelRailTape and ReelRailTape and ReelRailTape and ReelRailTape and Reel

CS8416-CSZCS8416-CSZRCS8416-CZZCS8416-CZZRCS8416-CNZCS8416-CNZRCS8416-DSZCS8416-DSZRCS8416-DZZCS8416-DZZRCS8416-DNZCS8416-DNZRCDB8416

DS578F359

元器件交易网www.cecb2b.com

CS8416

21.REVISION HISTORY

Release

Changes

-Reformatted “Features” on page1

-Added RMCK/OMCK maximum in“Switching Characteristics” on page8.

-Corrected AES3 Direct format in “Serial Audio Output Example Formats” on page24.-Corrected Table2 and page28 text referencing VCO idle frequency.-Added timing note to Figure 10 on page 32.

-Corrected “Control Port Description” on page33 to reflect the Auto-Increment function of the MAP.

-Added thermal relief pad label to QFN package in “Pin Description - Software Mode” on page12 and “Pin Description - Hardware Mode” on page16.

-Added “TSSOP Thermal Characteristics” on page57 and “QFN Thermal Characteristics” on page58.Clarified use of de-emphasis filter in AES3 direct-output format.Updated ordering information to include Automotive grade QFN option.

F2F3

Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com.

IMPORTANT NOTICECirrus Logic, Inc. and its subsidiaries (\"Cirrus\") believe that the information contained in this document is accurate and reliable. However, the information is subjectto change without notice and is provided \"AS IS\" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevantinformation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of salesupplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrusfor the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of thirdparties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consentdoes not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USEIN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE-VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER-STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED,INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCTTHAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICALAPPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS ANDOTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTIONWITH THESE USES.Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarksor service marks of their respective owners.AC-3 is a registered trademark of Dolby Laboratories, Inc. DTS is a registered trademark of the Digital Theater Systems, Inc.I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola Inc.60DS578F3

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