CLOCK JITTER COMPENSATED CLOCK CIRCUITS AND METHOD

专利名称：CLOCK JITTER COMPENSATED CLOCK

CIRCUITS AND METHODS FOR GENERATINGJITTER COMPENSATED CLOCK SIGNALS

发明人：Yantao Ma申请号：US12416822申请日：20090401

公开号：US20100253404A1公开日：20101007

专利附图：

摘要：Clock circuits, memories and methods for generating a clock signal are

described. One such clock circuit includes a delay locked loop (DLL) configured to receive

a reference clock signal and generate an output clock signal having an adjustable phaserelationship relative to the reference clock signal, and further includes a clock jitterfeedback circuit coupled to a clock tree and the DLL. The clock jitter feedback circuit isconfigured to synchronize a clock jitter feedback signal and a DLL feedback signal that isbased on the output clock signal. The clock jitter feedback circuit is further configured toprovide the clock jitter feedback signal to the DLL for synchronization with a bufferedreference clock signal. The clock jitter feedback signal is based on and generated inresponse to receiving a distributed output clock signal from the clock tree circuit and thebuffered reference signal is based on the reference clock signal.

申请人：Yantao Ma

地址：Boise ID US

国籍：US

更多信息请下载全文后查看