About This Guide
This user guide introduces the Virtex®-6 FPGA ML605 board features, provides instructions for setting up the hardware, and includes step-by-step procedures for verifying the ML605 board functionality.
Additional Documentation
ML605 Evaluation Kit Getting Started GuideUG533 (v1.5) October 20, 2011
Getting Started with PCI Express PIO Demonstration
Getting Started with PCI Express PIO Demonstration
The LogiCORE™ IP Virtex-6 Integrated Block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex-6 FPGA
devices. The Integrated Block for PCI Express solution supports 1-lane, 2-lane, 4- lane, and 8-lane Endpoint and Root Port configurations at up to Gen2 speed, all of which arecompliant with the PCI Express Base Specification, v2.0.
For information about the internal architecture of the Virtex-6 FPGA Integrated Block, see the LogiCORE™ IP Virtex-6 FPGA Integrated Block User Guide for PCI Express. [Ref18]Figure1-27 illustrates the interfaces to the core.
LogiCORE IP Virtex-6 FPGA Integrated Block for PCI ExpressTXBlock RAMRXBlock RAMUserLogicTransaction(TRN)Physical LayerControlandStatusHostInterfaceUserLogicPhysical(PL)Virtex-6 FPGA Integrated Block for PCI Express(PCIE_2_0)GTXTransceiversPCI Express(PCI_EXP)PCIExpressFabricConfiguration(CFG)Optional DebugUser LogicOptional Debug(DRP)System(SYS)ClockandResetUG533_11_101609Figure 1-27: Interfaces to the Core
The ML605 x8 PCI Express Gen 1 Programmed Input Output (PIO) design consists of a simple example that can accept read and write transactions and respond to requests. PIO transactions are generally used by a PCI Express system host CPU to access Memory Mapped Input Output (MMIO) and Configuration Mapped Input Output (CMIO)
locations in the PCI Express fabric. Endpoints for PCI Express accept Memory and IO Write transactions and respond to Memory and IO Read transactions with Completion with Data transactions.
The ML605 PIO example design is included with the Endpoint for PCIe generated by the CORE Generator, which allows users to easily bring up their system board with a known established working design to verify the link and functionality of the board.
The step-by-step procedure for creating the PIO design by Xilinx CORE Generator™ software is illustrated by the ML605 PCIe x8 Gen1 Design Creation tutorial [Ref 23]..
Virtex-6 Getting Started GuideUG533 (v1.5) October 20, 2011
Getting Started with the Base Reference Design
Getting Started with the Base Reference Design
The Base Reference Design targeting the ML605 evaluation board, will filter images that are transferred via Ethernet between the evaluation board and a PC. The images are stored in DDR3 SDRAM available on the evaluation board. The stored image is continuously read from SDRAM and filtered by the LX240T FPGA. The resulting image is continuously stored back in the DDR3 SDRAM. This filtered image is then retrieved by the Base Reference Design Interface Software and displayed on a PC.
Figure1-43 shows a block diagram of the base reference design that has been implemented in the Virtex-6 LX240T FPGA. The reference design includes common functions for Ethernet SGMII communication, external memory interface, UART, and control.
DDR3SystemMonitorSystem StatusEthernetPCPHYMDIOTEMAC_SINGLEGTXE1EmbeddedTri-ModeEthernetMACPacketProcessingEngineHostManagementPicoBlazeMIG Memory InterfaceSGMIIGammaImage ProcessingFIRFiltersInverseGammaDVIOutputEthernet ManagementLinkStatusLoopbackTestGTXTransceiver UG533_01_43_121109Figure 1-43:Base Reference Design Block Diagram
A DDR3 Memory Controller Block is used to store both the unfiltered and filtered images in the DDR3 SDRAM. These images are sent from a PC via a series of Ethernet packets. This memory controller is continuously reading, filtering, and storing images back into this memory. The PC also periodically retrieves the filtered images via Ethernet for display. The Ethernet Management section includes an on-chip hard coded MAC and a Packet Processing Engine. This section provides a way to control various aspects of the demo, transfer images between the demo board and a PC, and receive status from the demo. A simple MDIO controller is implemented using a Xilinx PicoBlaze™ processor. The purpose of this controller is to determine presence of an Ethernet link as well as its operating speed.The Image Processing structure consists of a 5x5 pixel 2D FIR filter.
Virtex-6 Getting Started GuideUG533 (v1.5) October 20, 2011
Getting Started with the Base Reference Design
Setting up the Hardware for the Base Reference Design
1.2.
Power-off the ML605
Connect one end of the provided Ethernet cable to the RJ45 connector P2 on the ML605and the other end to the Ethernet port on your PC. This connection will be used forcommunication between the ML605 board and your PC.Set the Ethernet Jumpers for SGMII mode
♦♦♦
3.
J66: Shunt over pins 2 and 3J67: Shunt over pins 2 and 3J68: No shunt
4.5.6.7.
Insert the provided CompactFlash (CF) card into the ML605 CF reader (U73)Set the SACE MODE switch S1 to 1011 (Position 4 to Position 1). This will configure theFPGA from the ACE file stored at configuration address 3 on the CF cardDo not change any other factory default settingsPower-on the ML605
Virtex-6 Getting Started GuideUG533 (v1.5) October 20, 2011
Getting Additional Help and Support
Getting Additional Help and Support
Support
For questions regarding products within your Product Entitlement Account or if you feel you have received this notification in error, send an email message to your regional Customer Service Representative:
Virtex-6 Getting Started GuideUG533 (v1.5) October 20, 2011
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